DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to a Restriction Requirement mailed on 07/07/2026, the Applicant elected without traverse Group I (claims 1-10) in a reply filed on 08/19/2026. Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim.
Currently, claims 1-10 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 06/04/2024. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Device Including Crystalline Oxide Semiconductor
(Clean Version) Semiconductor Device Including Crystalline Oxide Semiconductor
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0198534 A1 to Je et al. (“Je”).
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Regarding independent claim 1, Je in Fig. 3 teaches a semiconductor device 200 (Fig. 3 & ¶ 94, display device 200) comprising:
a first oxide semiconductor pattern 231a, 231d, 231f (Fig. 3, ¶ 106, a collective of second channel region 231a, second source region lower layer 231d and second drain region lower layer 231f of second active layer 231; ¶ 96, second active layer 231 is formed of an oxide semiconductor) disposed on a substrate 210, 211 (¶ 96, a collective of substrate 210 and buffer layer 211);
a gate pattern 215, 234 (Fig. 3, ¶ 99, a collective of second gate insulating layer 215 and second gate electrode 234) disposed on the first oxide semiconductor pattern 231a, 231d, 231f;
a second oxide semiconductor pattern 231e, 231g (Fig. 3, ¶ 101, a collective of second source region upper layer 231e and second drain region upper layer 231g of the second active layer 231; ¶ 96, second active layer 231 is formed of an oxide semiconductor) disposed on the first oxide semiconductor pattern 231a, 231d, 231f on both sides of the gate pattern 215, 234.
Regarding claim 2, Je in Fig. 3 further teaches an interlayer dielectric layer 216 (Fig. 3, ¶ 109, second interlayer insulating layer 216) that covers the gate pattern 215, 234; and
two contact holes (Fig. 3, ¶ 110, contact holes formed in the layer 216 that accommodate the second source electrode 232 and the second drain electrode 233) that pass through the interlayer dielectric layer 216 and expose the second oxide semiconductor pattern 231e, 231g on both sides of the gate pattern 215, 234 (Fig. 3, ¶ 109, ¶ 112).
Regarding claim 5, Je in Fig. 3 further teaches an interlayer dielectric layer 216 (Fig. 3, ¶ 96, second interlayer insulating layer 216) that covers the gate pattern 215, 234; and
two contact holes (Fig. 3, ¶ 110, a space formed in the layer 216 that accommodate the layers 231e and 232 and a space formed in the layer 216 that accommodate the layers 231g and 233) that expose the first oxide semiconductor pattern 231a, 231d, 231f on both sides of the gate pattern 215, 234,
wherein the second oxide semiconductor pattern 231e, 231g is formed inside a lower portion of each of the two contact holes (Fig. 3).
Regarding claim 6, Je in Fig. 3 further teaches a spacer 216 (Fig. 3, ¶ 96, second interlayer insulating layer 216) disposed on both sidewalls of the gate pattern 215, 234 covering both sidewalls of the gate pattern 215, 234,
wherein the second oxide semiconductor pattern 231e, 231g is separated from the gate pattern 215, 234 by the spacer 216 (Fig. 3).
Regarding claim 8, Je in Fig. 3 further teaches the first oxide semiconductor pattern 231a, 231d, 231f and the second oxide semiconductor pattern 231e, 231g include different constituent elements (¶ 102).
Regarding claim 9, Je in Fig. 3 further teaches the substrate 210, 211 includes an isolation layer 212-214 (Fig. 3, ¶ 96, a collective of first gate insulating layer 212, first interlayer insulating layer 213 and separation insulating layer 214),
wherein a height of a top surface of the substrate 210, 211 is lower than a height of a top surface of the isolation layer 212-214 (Fig. 3), and
wherein a height of a top surface of the first oxide semiconductor pattern 231a, 231d, 231f is equal to or less than the height of the top surface of the isolation layer 212-214 (Fig. 3).
Regarding claim 10, Je in Fig. 3 further teaches the second oxide semiconductor pattern 231e, 231g has a top surface that is higher than a bottom surface of the gate pattern 215, 234 (Fig. 3, bottom surface of the layer 215).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Je in view of US 2014/0127868 A1 to Saito et al. (“Saito”).
Regarding claim 3, Je in Fig. 3 further teaches two contact plugs 232, 233 (Fig. 3, ¶ 110, second source electrode 232 and second rain electrode 233) filled inside the two contact holes, respectively.
However, Je does not explicitly disclose said first and second oxide semiconductor patterns are crystalline.
Saito recognizes a need for providing an oxide semiconductor in which defects in the bulk can be further reduced and mobility would be higher (¶ 114). Saito satisfies the need by providing an oxide semiconductor having crystallinity (¶ 114), which includes a polycrystalline oxide semiconductor (¶ 103, ¶ 110-¶ 111).
Before the effective fling date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the first and second oxide semiconductor patterns taught by Je with the polycrystalline oxide semiconductor taught by Saito, so as to provide an oxide semiconductor in which defects in the bulk can be further reduced and mobility would be higher (Saito: ¶ 114).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 4 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 4, a storage element electrically connected to one of the two contact plugs; and wherein the storage element and the conductive line are disposed on the interlayer dielectric layer.
Claim 7 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, wherein the first oxide semiconductor pattern and the second oxide semiconductor pattern include same constituent elements, and no interface exists between the first oxide semiconductor pattern and the second oxide semiconductor pattern.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0005839 A1 to Daitoh et al. relates to an TFT including an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, and the oxide semiconductor includes a high mobility oxide semiconductor material.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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