DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 8/6/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 10-13 and 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ramachandran et al. (US Patent Application Publication No. 2016/0095221) (“Ramachandran”).
Regarding Claim 1, Ramachandran teaches a semiconductor structure comprising: a substrate (Figure 1, item 104), having a front surface (Figure 1, “active side”), a back surface (Figure 1, “Backside”) opposite to the front surface, and an active area (see depicted “active side”) at the front surface; a first through via (Figure 1, item 112), penetrating the substrate and having a top surface at the front surface of the substrate and a bottom surface at the back surface of the substrate (see Figure 1, item 112); a trench capacitor (Figure 1, item 114), extending from the back surface toward the front surface of the substrate (see Figure 1), wherein the trench capacitor is separated from the active area (see Figure 1); a first redistribution layer (RDL) (Figure 1, item 110b), disposed over the front surface of the substrate, and electrically connecting to the first through via, wherein the active area is disposed between the trench capacitor and the first RDL (see Figure 1); a second RDL (Figure 1, item 108d), disposed over the back surface of the substrate, and electrically connecting to the first through via and the trench capacitor (see Figure 1); a first contact feature (Figure 1, item depicted connected to 114), disposed over the second RDL and electrically connecting to the trench capacitor through the second RDL; and a first chip (Figure 2, item 208), bonded to the substrate over the front surface of the substrate.
Regarding Claim 2, Ramachandran further teaches a depth of the trench capacitor is substantially less than a depth of the first through via measured from the back surface of the substrate (see Figure 1).
Regarding Claim 5, Ramachandran further teaches a bonding layer (Figure 2, item between contacts 206), disposed over the first RDL and comprising a dielectric material (see Figure 2).
Regarding Claim 6, Ramachandran further teaches the bonding layer further comprises a metallic material (Figure 2, item 206) surrounded by the dielectric material and exposed through at a surface of the bonding layer opposite to the first RDL (see Figure 2).\
Regarding Claim 7, Ramachandran further teaches a second contact feature (Figure 2, item 108a), disposed over the second RDL and adjacent to the first contact feature, wherein the trench capacitor is disposed between the first contact feature and the second contact feature (see Figure 2).
Regarding Claim 10, Ramachandran further teaches a support substrate (Figure 2, item 202), disposed over the second RDL and electrically connecting the first chip through the contact feature (see Figure 2).
Regarding Claim 11, Ramachandran further teaches an interposer (Figure 2, item 106), disposed over the second RDL and bonded to the substrate through the contact feature, wherein the support substrate electrically connects to the first chip through the interposer (see Figure 2).
Regarding Claim 13, Ramachandran further teaches the second RDL includes a plurality of metal line layers, and a number of the metal line layers is less than 3 (Figure 2, items 108d – note 2 are depicted).
Regarding Claim 21, Ramachandran further teaches the first through via is disposed within a vertical projection of the first contact feature (see Figure 2).
Regarding Claim 22, Ramachandran further teaches the first through via is vertically aligned with the first contact feature (see Figure 2).
Regarding Claim 23, Ramachandran further teaches the substrate further comprises: an intrinsic area, disposed below the active area and being proximal to the back surface of the substrate, wherein the trench capacitor is disposed in the intrinsic area (see Figure 2, note “Trench Caps” area depicted).
Regarding Claim 24, Ramachandran further teaches the trench capacitor comprises: a first conductive layer, configured to receive a ground voltage through the first contact feature from the back surface of the substrate; and a second conductive layer electrically isolated from the first conductive layer, and configured to receive a positive voltage through the second contact feature from the back surface of the substrate (¶0037)
Regarding Claim 25, Ramachandran further teaches an interposer (Figure 3, item 308), wherein the substrate is bonded to the interposer through the first contact feature (see Figure 3); and at least a memory device, bonded to the interposer and being adjacent to the substrate (¶0045).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran as applied to Claim 1 above.
Regarding Claim 12, Ramachandran teaches Claim 1 as indicated above. Ramachandran does not specifically teach “a distance between an active region of the first chip and the active area of the substrate is less than 25 microns.” However, it would have been obvious to one of ordinary skill in the art at the time of effective filing to optimize the size of the chip structures, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Additionally, a change in size is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 U.S.P.Q. 237, CCPA 1955).
Claims 3, 4, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran as applied to Claim 1 above, and further in view of Yang et al. (US Patent Application Publication No. 2010/0144118) (“Yang”).
Regarding Claim 3, Ramachandran teaches Claim 1 as indicated above. Ramachandran does not specifically teach the first through via comprises a via dielectric layer and a via metal surrounded by the via dielectric layer. However, Yang teaches forming TSV structures with a metal core (Figure 1, item 113, ¶0024) and an outer barrier layer made of dielectric (Figure 1, item 111, ¶0023). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the structures described in Yang in the device of Ramachandran, as Yang teaches the structure allows for electrical communication through the TSV and it has been held that a conclusion of obviousness can be drawn from “combining prior art elements according to known methods to yield predictable results,” such as forming recesses in a interconnect area of a substrate, in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Regarding Claim 4, Ramachandran as modified by Yang further teaches the via metal is electrically isolated from the active area by the via dielectric layer (see Figure 1 of Ramachandran and Figure 1 of Yang with ¶0023 of Yang).
Regarding Claim 8, Ramachandran teaches Claim 8 as indicated above. Ramachandran does not specifically teach a second through via, penetrating the substrate and being adjacent to the first through via, wherein the trench capacitor is disposed between the first through via and the second through via. However, Yang teaches a second TSV structure on the opposite end of the chip (see Figure 1, note both instances of 113 with device elements located between the TSV, see item 104). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use additional TSV structures as taught in Yang in the device of Ramachandran, as doing so allows for additional electrical connections to be present between elements on opposite sides of the substrate and it has been held that a conclusion of obviousness can be drawn from “combining prior art elements according to known methods to yield predictable results,” such as forming recesses in a interconnect area of a substrate, in KSR International Co. v. Teleflex Inc., 550 U.S. 398, 420, 82 USPQ2d 1385, 1397 (2007).
Regarding Claim 9, Ramachandran as modified by Yang further teaches the first through via is aligned with the first contact feature along a vertical direction, and the second through via is aligned with a second contact feature, adjacent to the first contact feature, along the vertical direction (see Figure 2 of Ramachandran and Figure 1 of Yang, note the TSVs are depicted on opposite sides of the device).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. (US Patent Application Publication No. 2020/0402892)
Kao et al. (US Patent Application Publication No. 2020/0411636)
Chiu et al. (US Patent Application Publication No. 2022/0310471)
Wang et al. (US Patent Application Publication No. 2023/0062136)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST.
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MARK W. TORNOW
Primary Examiner
Art Unit 2891
/MARK W TORNOW/Primary Examiner, Art Unit 2891
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