DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 7/17/26.
Applicant’s election without traverse of Group I in the reply filed on 9/17/26 is acknowledged. Claims 16-20, which would have been withdrawn, have been canceled by Applicant.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/4/24 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 14-15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0098277 A1 (“Liu”).
Liu teaches, for example:
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Liu teaches:
A stacked field-effect transistor (FET) device (see e.g. Fig. 18; the labels in Liu are applied sparingly, so reference is made to earlier-cited figures where labels appear; see Office-annotated version of Fig. 18, above, where labels have been added for clarity) comprising:
a lower FET (e.g. 304) comprising
lower channel layers (some of which are labeled in annotated Fig. 18),
a lower gate structure (comprising at least the “lower gates” shown in annotated Fig. 18) that is between the lower channel layers, and
a lower source/drain (S/D) region (e.g. 1402 and/or 1404, see labels in Fig. 14; see annotated Fig. 18) that is electrically connected to the lower channel layers;
an S/D contact (e.g. 1602 and/or 1606) that is electrically connected to the lower S/D region;
an upper FET (e.g. 302) that is on top of the lower FET, the upper FET comprising
upper channel layers (some of which are labeled in annotated Fig. 18),
an upper gate structure (comprising at least the “upper gates” shown in annotated Fig. 18; also perhaps comprising the “dummy or metal gate structure 306”, see e.g. para 53 and see label in Fig. 17; see also annotated Fig. 18) that is between the upper channel layers, and
an upper S/D region (comprising one or more of the elements 802, see e.g para 63 and label in e.g. Figs. 8 and 13; and/or one or more of the elements 1308, see e.g. para 74 and Fig. 13; see also annotated Fig. 18) that is electrically connected to the upper channel layers,
wherein the upper gate structure comprises
a conductive gate (1802 itself is a “metal gate structure”, see e.g. para 80; 306 itself may be a “dummy or metal gate structure”, see e.g. para 53) and
an isolation region (comprising, e.g. one or more of the spacers 702, see label in Fig. 6; see annotated Fig. 18; and/or comprising e.g. isolation 1002, see label in Fig. 10; see annotated Fig. 18) that is inside the conductive gate and on a sidewall of the S/D contact,
Note: the way that the “upper gate structure comprises…” limitation is claimed, wherein the upper gate structure comprises a conductive gate but also a separate “isolation region”, is unusual. Applicant’s isolation region is not an element typically associated with a gate electrode, such as a thin gate insulating layer. Rather, it is 136, which can be seen in Figs. 1D and 1E, and is rather separate from the gate metal 170a itself, and is much more akin in the art to an “interlayer dielectric” (ILD) or insulating “spacer”. For example, there is nothing that would have constrained Applicant from calling 138, 130, 132 as being part of this gate structure, though they labeled those insulating layers as separate layers. As such, there is nothing in the term that confines a “gate structure” from reasonably comprising many different features, such as other insulating layers or elements, such as ILD layers, spacers layers, etch-stop layers, etc., and could specifically involve multiple of them. In Liu, there are indeed many insulating layers between the upper gate electrodes (and/or between the upper gate and the lower gate), such as e.g. 1002, 702, 604, 504, 210, and 308.
Furthermore, the description of the isolation region being “inside the conductive gate” is an odd usage of the term “inside”. One can see that in Fig. 1E, isolation region 136 is next to conductive gates 174a, but is not “inside” it like water is inside a cup, or like a present is within a wrapped box, because there is no bottom or top to the conductive gate 170a over or under 136. Hence, it is reasonable to interpret Liu’s geometry as meeting the claimed limitation because parts of the isolation region, such as 604, and/or 702, and/or 1002 are laterally between multiple gates 170a, and are on sidewalls of S/D contacts 1602 and/or 1606);
a spacer (comprising e.g. one or more of 308, 504, and 210; for “dielectric portion 308”, see label in Fig. 3 and in annotated Fig. 18; for “ILD portion 504”, see label in Fig. 9 and in annotated Fig. 18; for spacer 210, see Fig. 3 and annotated Fig. 18) that separates the upper channel layers from the lower channel layers; and
an insulating layer (comprising e.g. parts of spacer 604, and/or isolation 1002, and/or 504, and/or 210; for spacer 604, see label in Fig. 6, and also see annotated Fig. 18; for 1002, see label in Fig. 10, and also see annotated Fig. 18) that is between a lower surface of the isolation region and an upper surface of the lower gate structure (at least portions of 604 are on the bottom of 702, and thus between the bottom of 702 and the top of the lower gate; also, portions of 1002 near its bottom are spaced such that a line between the bottom of 702 and a top of the lower gate passes through 1002; also, portions of 504 are spaced such that a line between the bottom of 702 and a top of the lower gate passes through 504).
2. The stacked FET device of claim 1, wherein the insulating layer does not vertically overlap the lower channel layers in a vertical direction that is perpendicular to the upper surface of the lower gate structure (see e.g. annotated Fig. 18, wherein at least portions of 604, 504, 210 are not vertically above the lower channel layers).
3. The stacked FET device of claim 1, wherein a sidewall of the conductive gate is in contact with a sidewall of the isolation region (see e.g. annotated Fig. 18).
4. The stacked FET device of claim 1,
wherein the insulating layer is thinner, in a vertical direction, than the spacer (see e.g. annotated Fig. 18, wherein e.g. 210 and 604 are each thinner vertically than is 504),
wherein the insulating layer is thinner, in the vertical direction, than the isolation region (see e.g. annotated Fig. 18, wherein e.g. 210 and 604 are each thinner vertically than is 702), and
wherein the vertical direction is perpendicular to the upper surface of the lower gate structure.
5. The stacked FET device of claim 1, wherein the lower surface of the isolation region comprises: a first portion that is on an upper surface of the spacer; and a second portion that is on an upper surface of the insulating layer (see e.g. annotated Fig. 18).
6. The stacked FET device of claim 1, wherein the isolation region comprises: a first portion that vertically overlaps the spacer and the lower channel layers in a vertical direction that is perpendicular to the upper surface of the lower gate structure; and a second portion that vertically overlaps the insulating layer in the vertical direction and does not vertically overlap the lower channel layers in the vertical direction (see e.g. annotated Fig. 18).
14. A stacked field-effect transistor (FET) device (see e.g. Fig. 18; the labels in Liu are applied sparingly, so reference is made to earlier-cited figures where labels appear; see Office-annotated version of Fig. 18, above, where labels have been added for clarity) comprising:
a lower FET (e.g. 304) comprising lower channel layers (some of which are labeled in annotated Fig. 18), a lower gate structure (comprising at least the “lower gates” shown in annotated Fig. 18) and a lower gate structure (comprising at least the “lower gates” shown in annotated Fig. 18) that is between the lower channel layers;
a contact (e.g. 1602 and/or 1606) that is electrically connected to the lower FET;
an upper FET (e.g. 302) that is on top of the lower FET, the upper FET comprising upper channel layers (some of which are labeled in annotated Fig. 18) and an upper gate structure (comprising at least the “upper gates” shown in annotated Fig. 18; also perhaps comprising the “dummy or metal gate structure 306”, see e.g. para 53 and see label in Fig. 17; see also annotated Fig. 18) that is between the upper channel layers,
wherein the upper gate structure comprises a conductive gate (1802 itself is a “metal gate structure”, see e.g. para 80; 306 itself may be a “dummy or metal gate structure”, see e.g. para 53) and an isolation region (comprising, e.g. one or more of the spacers 702, see label in Fig. 6; see annotated Fig. 18; and/or comprising e.g. isolation 1002, see label in Fig. 10; see annotated Fig. 18) that is between a first portion and a second portion of the conductive gate and on a sidewall of the contact;
[Note: the way that the “upper gate structure comprises…” limitation is claimed, wherein the upper gate structure comprises a conductive gate but also a separate “isolation region”, is unusual. Applicant’s isolation region is not an element typically associated with a gate electrode, such as a thin gate insulating layer. Rather, it is 136, which can be seen in Figs. 1D and 1E, and is rather separate from the gate metal 170a itself, and is much more akin in the art to an “interlayer dielectric” (ILD) or insulating “spacer”. For example, there is nothing that would have constrained Applicant from calling 138, 130, 132 as being part of this gate structure, though they labeled those insulating layers as separate layers. As such, there is nothing in the term that confines a “gate structure” from reasonably comprising many different features, such as other insulating layers or elements, such as ILD layers, spacers layers, etch-stop layers, etc., and could specifically involve multiple of them. In Liu, there are indeed many insulating layers between the upper gate electrodes (and/or between the upper gate and the lower gate), such as e.g. 1002, 702, 604, 504, 210, and 308.
It is reasonable to interpret Liu’s geometry as meeting the claimed limitation because parts of the isolation region, such as 604, and/or 702, and/or 1002 are laterally between multiple gates 170a, and are on sidewalls of S/D contacts 1602 and/or 1606)]
a spacer (comprising e.g. one or more of 308, 504, and 210; for “dielectric portion 308”, see label in Fig. 3 and in annotated Fig. 18; for “ILD portion 504”, see label in Fig. 9 and in annotated Fig. 18; for spacer 210, see Fig. 3 and annotated Fig. 18) that separates the upper channel layers from the lower channel layers; and
an insulating layer (comprising e.g. parts of spacer 604, and/or isolation 1002, and/or 504, and/or 210; for spacer 604, see label in Fig. 6, and also see annotated Fig. 18; for 1002, see label in Fig. 10, and also see annotated Fig. 18) that is between a lower surface of the isolation region and an upper surface of the lower gate structure (at least portions of 604 are on the bottom of 702, and thus between the bottom of 702 and the top of the lower gate; also, portions of 1002 near its bottom are spaced such that a line between the bottom of 702 and a top of the lower gate passes through 1002; also, portions of 504 are spaced such that a line between the bottom of 702 and a top of the lower gate passes through 504).
15. The FET device of claim 14, wherein the contact is a first contact among a pair of source/drain (S/D) contacts (1602 and 1606) that are electrically connected to a pair of S/D regions, respectively, of the lower FET, and wherein the isolation region is between the pair of S/D contacts (see annotated Fig. 18).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu.
Re claim 11, Liu teaches claim 1, as discussed above, but does not explicitly teach wherein the isolation region (e.g. 702) has a lower dielectric constant than the insulating layer (e.g. isolation 1002 can comprise one of multiple materials such as polyimide, silicon oxide, or silicon nitride, see e.g. para 68) (no material of 702 is explicitly disclosed, hence no teachings about the dielectric constant are taught).
However, one of ordinary skill in the art would have found it obvious to use a similar material for the spacer layer, given that Liu teaches that the device should include various spacer layers, interlayer dielectrics, and the like (see e.g. para 53), and has equated the spacer with insulating barriers (see e.g. para 54), that spacers can be made of nitrides (see e.g. para 59) or polyimide, SiN, or silicon dioxide (see e.g. para 68). Hence, the materials of the various insulating layers are obvious to be selected from the well-known materials such as those disclosed, and in various combinations, the claimed relationship between the dielectric constant would be met.
Applicant has not disclosed that the claimed dielectric constants (and the materials which provide such properties) are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Re claim 12, Liu teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention wherein the insulating layer is an etch-stop layer that comprises silicon nitride (see e.g. para 68, wherein 1002 may be SiO2; hence, it may be used as an etch stop for other materials).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of US 2022/0336456 A1 (“Hong”).
Re claim 13, Liu teaches claim 1, as discussed above, but does not explicitly teach wherein the conductive gate comprises a first conductive material that is different from a second conductive material of the lower gate structure.
Hong teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Liu wherein the conductive gate comprises a first conductive material that is different from a second conductive material of the lower gate structure (see e.g. para 49; see claim 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Hong to the invention of Liu. The motivation to do so is that the combination produces the predictable results of optimizing the materials of the gate electrode’s metals and/or workfunction layers depending on the desired device conductive types and/or characteristics (para 49; see e.g. para 22 wherein TRU may be p-type and TRN would be n-type, and hence the workfunction layers would be chosen of different materials to provide this difference).
Allowable Subject Matter
Claim(s) 7-10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 1, 6, and 7, including:
wherein the spacer is a lateral portion of a first insulating material, wherein the insulating layer comprises a second insulating material that is different from the first insulating material, wherein the isolation region comprises a third insulating material that is different from the first insulating material and different from the second insulating material, wherein a vertical portion of the first insulating material is between, in a lateral direction that is perpendicular to the vertical direction, a third portion of the isolation region and the sidewall of the S/D contact, and wherein the vertical portion of the first insulating material extends longitudinally in the vertical direction.
The other claims 8-10 each depend from claim 7, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
US 2023/0275123 (“Liu”) teaches insulating layers 134, 132, 116, 98, 152 on and between gate electrodes 154 and S/D contacts 174 (see e.g. Fig. 21C).
US 2024/0186325 A1 (“Motoyama”) teaches a stacked device having insulating layers 134, 122, on and between gates 110 and S/D contacts 140 (Figs. 31-35)
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
