DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant’s election without traverse of Group II, Species IIa, claims 1-18 & 20 in the reply filed on 8/11/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0169999) in view of Jeon et al. (US 2012/0173956).
Re claim 1, Kim teaches, under BRI, Figs. 1-8, [0065, 0079, 0080, 0084], a memory device, comprising:
-a first semiconductor layer (CELL) including:
a memory cell array (110) connected to a plurality of wordlines (WL) and a plurality of bitlines (BL), the memory cell array (110) including a plurality of normal memory cells (MC) configured to store normal data, the plurality of wordlines (WL) extending in a first direction (y axis), the plurality of bitlines (BL) extending in a second direction (x axis) intersecting the first direction (Figs. 4-6); and
-a second semiconductor layer (PERI) on the first semiconductor layer (CELL) in a third direction perpendicular (z axis) to the first direction and the second direction (Figs. 1 & 7A), the second semiconductor layer (PERI) including:
a peripheral circuit (PERI) configured to control the memory cell array (110), the peripheral circuit including a row decoder (XDEC), and
wherein at least a portion of a region including the plurality of memory cells (110) in the first semiconductor layer (CELL) and at least a portion of a region including the row decoder (XDEC) in the second semiconductor layer (PERI) at least partially overlap in a plan view (Figs. 1 & 7A).
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Kim does not explicitly teach a plurality of error correction code (ECC) memory cells configured to store ECC data; and at least a portion of a region including the plurality of ECC memory cells in the first semiconductor layer and at least a portion of a region including the row decoder in the second semiconductor layer at least partially overlap in a plan view.
Jeon teaches, under BRI, Fig. 2, [0034, 0039], a plurality of error correction code (ECC) memory cells (124) configured to store ECC data; and at least a portion of a region including the plurality of ECC memory cells (124) in the first semiconductor layer and at least a portion of a region including the row decoder (125) in the second semiconductor layer at least partially overlap in a plan view (in x axis).
As taught by Jeon, one of ordinary skill in the art would utilize & modify the above teaching into Kim to obtain ECC memory cells and partially overlapping between the ECC memory cells and region including the row decoder as claimed, because it aids in improving data correction & performance of the memory device/system. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Jeon in combination with Kim due to above reason.
Re claim 18, Kim teaches, Fig. 14A, [0143], wherein the first semiconductor layer (CELL) further includes a first bonding pad (1872a), wherein the second semiconductor layer (PERI) further includes a second bonding pad (1771a) electrically connected to the first bonding pad, and wherein the first and second semiconductor layers are electrically connected in the third direction (z axis) by the first and second bonding pads (1771a, 1872a).
Allowable Subject Matter
3. Claims 2-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed. The allowed subject matter includes: “wherein the memory cell array includes: a plurality of normal memory cells…wherein the peripheral circuit includes…to the second region in the semiconductor layer”.
Additional prior arts include: Radke (US 2016/0253237, Figs. 1 & 5) discloses apparatus and method including correction code organization; Vogelsang (US 8,473,808, Figs. 1 & 2) discloses memory chip including error correction circuitry configured to receive data words from external device; Lim et al. (US 2017/0330624, Fig. 1, 2 & 7A) discloses a vertical structure include row decoder disposed under a memory cell array; Oh et al. (US 9,165,654, Fig. 1) discloses memory device includes upper layer with cell array and lower layer with page buffer control circuit; and Yamazaki et al. (US 8,508,967, Figs. 1 & 2A) discloses a semiconductor device including memory cell array in upper portion and row decodes in lower portion, individually or in combination, do not meet all limitations cited above.
Conclusion
4. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kang et al. (US 2010/0223532, Fig. 1) discloses semiconductor memory device including a plurality memory cells, ECC cells, row & column decoders.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/25/26
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