DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 and 9-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchimochi (US Pub. 2019/0103340).
Regarding Claim 1, Tsuchimochi discloses a semiconductor module, comprising: a power electronic substrate 26 comprising a first conductive layer 36, a second conductive layer 38, and an insulating layer 34 separating the first and second conductive layers (36, 38) (page 3, paragraph 40); at least one semiconductor die 20 (page 3, paragraph 36) arranged over the first conductive layer 36 (see fig. 4); and a molded body 12 (page 3, paragraph 35) comprising a first side 12a and an opposite second side 12b (see fig. 4), the molded body 12 encapsulating the at least one semiconductor die 20 and partially encapsulating the power electronic substrate 26 such that the second conductive layer 38 is at least partially exposed from the second side 12b of the molded body 12 (page 3, paragraph 42; see fig. 4), wherein the insulating layer 34 protrudes beyond a contour of the first conductive layer 36 and/or beyond a contour of the second conductive layer 38 at lateral sides of the power electronic substrate 26 by a nonzero protrusion (see figs. 4-5B).
Tsuchimochi fails to disclose explicitly wherein a ratio of a thickness of the insulating layer to a length of the protrusion is 0.8 or more.
However, the application itself explains that a comparatively large ratio of the thickness of the insulating layer to the length of the protrusion may reduce or at least homogenize the bending stress at the edge of the insulating layer and thereby reduce or eliminate the occurrence of cracks in the insulating layer. Thus, the application identifies the claimed ratio merely as affecting a known performance characteristic, namely the reduction of mechanical stress and cracking.
Furthermore, the application does not demonstrate that the claimed ratio of 0.8 or more is critical or yields any unexpected results over other values. In the absence of evidence of criticality or unexpected results, selecting ratio of 0.8 or more would have been an obvious matter of routine optimization to achieve the expected benefit of reduced bending stress and crack formation. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to adjust the relative dimensions of the insulating layer thickness and protrusion length to achieve improved mechanical reliability, including reducing stress concentration and preventing crack formation, through routine experimentation and optimization of known result-effective variables.
Regarding Claim 2, Tsuchimochi discloses wherein the first conductive layer 36 and the second conductive layer 38 have different edge lengths (see figs 5A and 5B), and wherein the length of the protrusion is calculated with respect to the conductive layer with the larger edge length (see motivation statements stated in the rejection of claim 1 above).
Regarding Claim 3, Tsuchimochi discloses wherein the first conductive layer 36 has a smaller edge length than the second conductive layer 38 (see fig. 5A).
Regarding Claim 4, Tsuchimochi discloses wherein the edge length of the first conductive layer 36 is at least 0.3 mm smaller than the edge length of the second conductive layer 38 (see motivation statements stated in the rejection of claim 1 above).
Regarding Claim 5, Tsuchimochi discloses wherein the contour of the first conductive layer 36 and the contour of the second conductive layer 38 are congruent (see fig. 4).
Regarding Claim 9, Tsuchimochi discloses wherein the second conductive layer 38 is configured to be sintered or soldered to a heatsink 70 (page 5, paragraph 56; see fig. 7).
Regarding Claim 10, Tsuchimochi discloses wherein the length of the protrusion is 0.7 mm or less (see motivation statements stated in the rejection of claim 1 above).
Regarding Claim 11, Tsuchimochi discloses wherein the length of the protrusion is 0.2 mm or less (see motivation statements stated in the rejection of claim 1 above).
Regarding Claim 12, Tsuchimochi discloses a power electronic substrate 26 configured for use in a semiconductor module 10, the power electronic substrate 26 comprising: a first conductive layer 36 (page 3, paragraph 40); a second conductive layer 38 (page 3, paragraph 40); and an insulating layer 34 separating the first and second conductive layers (36, 38) (page 3, paragraph 40), wherein the insulating layer 34 protrudes beyond a contour of the first conductive layer 36 and/or beyond a contour of the second conductive layer 38 at lateral sides of the power electronic substrate 26 by a nonzero protrusion (see figs. 4-5B).
Tsuchimochi fails to disclose explicitly wherein a ratio of a thickness of the insulating layer to a length of the protrusion is 0.8 or more.
However, the application itself explains that a comparatively large ratio of the thickness of the insulating layer to the length of the protrusion may reduce or at least homogenize the bending stress at the edge of the insulating layer and thereby reduce or eliminate the occurrence of cracks in the insulating layer. Thus, the application identifies the claimed ratio merely as affecting a known performance characteristic, namely the reduction of mechanical stress and cracking.
Furthermore, the application does not demonstrate that the claimed ratio of 0.8 or more is critical or yields any unexpected results over other values. In the absence of evidence of criticality or unexpected results, selecting ratio of 0.8 or more would have been an obvious matter of routine optimization to achieve the expected benefit of reduced bending stress and crack formation. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to adjust the relative dimensions of the insulating layer thickness and protrusion length to achieve improved mechanical reliability, including reducing stress concentration and preventing crack formation, through routine experimentation and optimization of known result-effective variables.
Regarding Claim 13, Tsuchimochi discloses wherein the power electronic substrate 26 is a direct copper bonded substrate, a direct aluminum bonded substrate, or an active metal brazed substrate (page 2, paragraph 29; page 3, paragraph 41).
Regarding Claim 14, Tsuchimochi discloses a method for fabricating a semiconductor module 10, the method comprising: providing a power electronic substrate 26 comprising a first conductive layer 26, a second conductive layer 38, and an insulating layer 34 separating the first and second conductive layers (36, 38) (page 3, paragraph 40); arranging at least one semiconductor die 20 (page 3, paragraph 36) over the first conductive layer 36 (see fig. 4); and encapsulating the at least one semiconductor die 20 and partially encapsulating the power electronic substrate 26 with a molded body 12 (page 3, paragraph 35) comprising a first side 12a and an opposite second side 12b, such that the second conductive layer 38 is at least partially exposed from the second side 12b of the molded body 12 (page 3, paragraph 42; see fig. 4), wherein the insulating layer 34 protrudes beyond a contour of the first conductive layer 36 and/or beyond a contour of the second conductive layer 38 at lateral sides of the power electronic substrates 26 by a nonzero protrusion (see figs. 4-5B).
Tsuchimochi fails to disclose explicitly wherein a ratio of a thickness of the insulating layer to a length of the protrusion is 0.8 or more.
However, the application itself explains that a comparatively large ratio of the thickness of the insulating layer to the length of the protrusion may reduce or at least homogenize the bending stress at the edge of the insulating layer and thereby reduce or eliminate the occurrence of cracks in the insulating layer. Thus, the application identifies the claimed ratio merely as affecting a known performance characteristic, namely the reduction of mechanical stress and cracking.
Furthermore, the application does not demonstrate that the claimed ratio of 0.8 or more is critical or yields any unexpected results over other values. In the absence of evidence of criticality or unexpected results, selecting ratio of 0.8 or more would have been an obvious matter of routine optimization to achieve the expected benefit of reduced bending stress and crack formation. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to adjust the relative dimensions of the insulating layer thickness and protrusion length to achieve improved mechanical reliability, including reducing stress concentration and preventing crack formation, through routine experimentation and optimization of known result-effective variables.
Regarding Claim 15, Tsuchimochi discloses wherein the second conductive layer 38 is configured to be sintered or soldered to a heatsink 70 (page 5, paragraph 56; see fig. 7).
Regarding Claim 16, Tsuchimochi fails to disclose explicitly wherein the first conductive layer and/or the second conductive layer has a thickness of 0.25 mm or more.
However, the application does not demonstrate that the claimed thickness of 0.25 mm or more is critical or that it produces any unexpected results over other thicknesses, nor does the application identify any particular significance associated with the claimed value. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness of the first conductive layer and/or the second conductive layer, including selecting a thickness of 0.25 mm or more, through routine experimentation to obtain suitable substrate reducing thermal stress (Tsuchimochi; page 5, paragraph 55).
Regarding Claim 17, Tsuchimochi discloses wherein the insulating layer 34 has a thickness of 0.3 mm or more (see motivation statements stated in the rejection of claim 14 above).
Regarding Claim 18, Tsuchimochi discloses wherein the ratio is 1.0 or more (see motivation statements stated in the rejection of claim 14 above).
Regarding Claim 19, Tsuchimochi discloses wherein the ratio is 1.2 or more (see motivation statements stated in the rejection of claim 14 above).
Claims 1 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sakakibara et al. (US Pub. 2022/0278006; hereinafter “Sakakibara”).
Regarding Claim 1, Sakakibara discloses a semiconductor module, comprising: a power electronic substrate 20 comprising a first conductive layer 24, a second conductive layer 26, and an insulating layer 22 separating the first and second conductive layers (24, 26) (page 3, paragraph 38); at least one semiconductor die 12 (page 3, paragraph 34) arranged over the first conductive layer 24 (see fig. 3); and a molded body 52 (page 3, paragraph 33) comprising a first side 52a and an opposite second side 52b (see fig. 3), the molded body 52 encapsulating the at least one semiconductor die 12 and partially encapsulating the power electronic substrate 20 such that the second conductive layer 26 is at least partially exposed from the second side 52b of the molded body 52 (page 3, paragraph 38; see fig. 3), wherein the insulating layer 22 protrudes beyond a contour of the first conductive layer 24 and/or beyond a contour of the second conductive layer 26 at lateral sides of the power electronic substrate 20 by a nonzero protrusion (see figs. 3 and 7-10).
Tsuchimochi fails to disclose explicitly wherein a ratio of a thickness of the insulating layer to a length of the protrusion is 0.8 or more.
However, the application itself explains that a comparatively large ratio of the thickness of the insulating layer to the length of the protrusion may reduce or at least homogenize the bending stress at the edge of the insulating layer and thereby reduce or eliminate the occurrence of cracks in the insulating layer. Thus, the application identifies the claimed ratio merely as affecting a known performance characteristic, namely the reduction of mechanical stress and cracking.
Furthermore, the application does not demonstrate that the claimed ratio of 0.8 or more is critical or yields any unexpected results over other values. In the absence of evidence of criticality or unexpected results, selecting ratio of 0.8 or more would have been an obvious matter of routine optimization to achieve the expected benefit of reduced bending stress and crack formation. Accordingly, the claim is prima facie obvious unless the claimed variables produce unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to adjust the relative dimensions of the insulating layer thickness and protrusion length to achieve improved mechanical reliability, including reducing stress concentration and preventing crack formation, through routine experimentation and optimization of known result-effective variables.
Regarding Claim 6, Sakakibara discloses wherein the first conductive layer 24 and/or the second conductive layer 26 comprises a taper at the lateral sides of the power electronic substrate 20 (see fig. 9D).
Regarding Claim 7, Sakakibara discloses wherein the taper has an angle (C1) of 30° or more with respect to a plane which is perpendicular to the first and/or second conductive layer (24, 26) (45 degrees or more and smaller than 90 degrees; page 5, paragraph 51).
Regarding Claim 8, Sakakibara discloses wherein the angle is 45° or more (45 degrees or more and smaller than 90 degrees; page 5, paragraph 51).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEUNG LEE whose telephone number is (571)272-5977. The examiner can normally be reached 9 AM - 5:30 PM.
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 June 9, 2026
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