DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4,8,9, 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US-20220085048-A1; Lee) in view of Sun et al. ( US-20230178595-A1; Sun).
Regarding claim 1, Lee discloses a semiconductor memory device comprising: a cell region (Fig. 2, CAS; ¶44); and a peripheral circuit region (Fig. 2, PCS; ¶44) electrically connected with the cell region, wherein the cell region includes a plurality of gate electrodes (Fig. 7B, 130; ¶59) spaced apart from each other, the plurality of gate electrodes stacked in a vertical direction, and a channel structure (Fig. 7B, 180; ¶86) extending through the plurality of gate electrodes in the vertical direction, wherein the peripheral circuit region includes a substrate, (Fig. 7B, 210; ¶70) a first element isolation structure(Fig. 7B, 202 associated with PA; ¶120) defining a first active region in the substrate, the first element isolation structure extending to a first depth, a first gate structure (Fig. 7B, 220A associated with PA; ¶70) on the first active region, a second element isolation structure (Fig. 7B, 202 associated with CON; ¶120) defining a second active region (Fig. 7B,PAC associated with CON; ¶120) in the substrate, the second element isolation structure extending to a second depth larger than the first depth, a second gate structure (Fig. 7B, 220B; ¶70) on the second active region, a third element isolation structure (Fig. 7B, 202 associated with MEC ¶120) defining a third active region (Fig. 7B, PAC associated with MEC; ¶120) in the substrate,…and a third gate structure (Fig. 7B, 220C; ¶70) on the third active region,
Lee is silent on the third element isolation structure including a first element isolation pattern and a second element isolation pattern, the first element isolation pattern extending to a third depth, and the second element isolation pattern extending to a fourth depth larger than the third depth inside the first element isolation pattern, … wherein the first element isolation pattern and the second element isolation pattern include different materials from each other.
Sun discloses a memory device comprising a plurality of isolation structures where a third element isolation structure (Fig.3, 27; ¶47-48) including a first element isolation pattern (Fig.3, 15; ¶47-48) and a second element isolation pattern (Fig.3, 24; ¶47-48), the first element isolation pattern extending to a third depth, and the second element isolation pattern extending to a fourth depth larger than the third depth inside the first element isolation pattern, … wherein the first element isolation pattern and the second element isolation pattern include different materials from each other. (¶48)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use the isolation structure of Sun to increase the etch rate of the isolation structure.
Regarding claim 2, Lee in view of Sun discloses the semiconductor memory device of claim 1, wherein the first depth of the first element isolation structure (Fig. 3, 115; ¶44 Sun) is the same as the third depth of the first element isolation pattern.(Fig.3, 15; ¶47-48 Sun)
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to adjust the size of the first isolation structure for improved reliability. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device.
MPEP 2144.04 (IV)(A)
Regarding claim 3, Lee in view of Sun discloses the semiconductor memory device of claim 1, wherein the fourth depth of the second element isolation pattern (Fig.3, 24; ¶47-48 Sun) is smaller than or equal to the second depth of the second element isolation structure. (Fig.3, 136; ¶44 Sun)
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to adjust the size of the first isolation structure for improved reliability. Also, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device.
MPEP 2144.04 (IV)(A)
Regarding claim 4, Lee in view of Sun discloses the semiconductor memory device of claim 1, wherein a width of the first element isolation structure (Fig. 7B, 202 associated with PA; ¶120 Lee) is larger than a width of the second element isolation structure.(Fig. 7B, 202 associated with CON; ¶120 Lee)
Regarding claim 5, Lee in view of Sun discloses the semiconductor memory device of claim 1, wherein a width of the first element isolation pattern (Fig. 2A, 15; ¶46 Sun) is larger than a width of the second element isolation pattern. (Fig. 2A, 24; ¶46 Sun)
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to have the isolation structure configuration of Sun for improved reliability.
Regarding claim 8, Lee in view of Sun discloses the semiconductor memory device of claim 1, wherein the first element isolation structure (Fig. 2A, 115; ¶48 Sun) includes a different material from the second element isolation structure. (Fig. 2A, 24; ¶48 Sun)
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to have the isolation structure configuration of Sun for improved reliability.
Regarding claim 9, Lee in view of Sun discloses the semiconductor memory device of claim 1, wherein the substrate includes a fence pattern (Fig. 5, theta2; ¶68 Sun) in at least a part between the first element isolation pattern (Fig. 5, 15; ¶66 Sun) and the second element isolation pattern (Fig. 5, 24 ¶66 Sun), and wherein a width of the fence pattern decreases toward an upper side of the substrate.
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to have the isolation structure configuration of Sun for improved reliability.
Regarding claim 11, Lee discloses a semiconductor memory device comprising:
a cell region (Fig. 2, CAS; ¶44); and a peripheral circuit region (Fig. 2, PCS; ¶44) electrically connected with the cell region, wherein the cell region includes a plurality of gate electrodes (Fig. 7B, 130; ¶59) spaced apart from each other, the plurality of gate electrodes stacked in a vertical direction, and a channel structure (Fig. 7B, 180; ¶86) extending through the plurality of gate electrodes in the vertical direction, wherein the peripheral circuit region includes a substrate (Fig. 7B, 210; ¶70) including a first side (top or bottom) and a second side (top or bottom), the first side and the second side opposite to each other, a first element isolation structure (Fig. 7B, 202 associated with PA; ¶120) defining a first active region (Fig. 7B, PAC associated with PA; ¶120) in the substrate, the first element isolation structure in a first trench having a first width, a first gate structure (Fig. 7B, 220A associated with PA; ¶70) extending in a direction (Y) intersecting the first active region, the first gate structure being on the first active region, a second element isolation structure (Fig. 7B, 202 associated with CON; ¶120) defining a second active region (Fig. 7B, PAC associated with CON; ¶120) in the substrate, the second element isolation structure in a second trench having a second width, the second width being smaller than the first width, a second gate structure extending in a direction intersecting the second active region, the second gate structure (Fig. 7B, 220B; ¶70) being on the second active region, a third element isolation structure (Fig. 7B, 202 associated with MEC; ¶120) defining a third active region (Fig. 7B, PAC associated with MEC; ¶120) in the substrate, …a third gate structure (Fig. 7B, 220C; ¶70) extending in a direction intersecting the third active region, the third gate structure being on the third active region,…
Lee is silent on the third element isolation structure in a third trench having a third width and a fourth trench having a fourth width, the fourth width being smaller than the third width, and … wherein a bottom side of the fourth trench is closer to the first side of the substrate than a bottom side of the second trench.
Sun discloses a memory device comprising a plurality of isolation structures where a third isolation structure (Fig.3, 27; ¶47-48) comprises a second isolation pattern (Fig.3, 24; ¶47-48) extending through a first isolation pattern (Fig.3, 15; ¶47-48) through third and fourth trenches, the fourth width being smaller than the third width, and wherein a bottom side of the fourth trench is closer to the first side of the substrate than a bottom side of a second trench. (Fig.3, 136; ¶47-48)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use the isolation structure of Sun to increase the etch rate of the isolation structure.
Regarding claim 12, Lee in view of Sun discloses semiconductor memory device of claim 11, wherein a depth of the first trench (Fig. 3, 115; ¶44 Sun) is the same as a depth of the third trench. (Fig.3, 15; ¶47-48 Sun)
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to have the isolation structure configuration of Sun for improved reliability.
Regarding claim 13, Lee in view of Sun discloses semiconductor memory device of claim 11, wherein a depth of the fourth trench (Fig.3, 24; ¶47-48 Sun) is smaller than a depth of the second trench. (Fig.3, 136; ¶44 Sun)
Before the effective filing date of the invention it would have been obvious to one of ordinary skill in the art to have the isolation structure configuration of Sun for improved reliability.
Regarding claim 14, Lee in view of Sun discloses semiconductor memory device of claim 11, wherein the third element isolation structure comprises a first element isolation pattern (Fig.3, 15; ¶47-48 Sun) in the third trench, and a second element isolation pattern (Fig.3, 24 ¶47-48 Sun) in the fourth trench, wherein the first element isolation pattern and the second element isolation pattern include different materials from each other.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use the isolation configuration of Sun to optimize threshold voltage stability.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US-20220085048-A1; Lee) in view of Sun et al. ( US-20230178595-A1; Sun) and further in view of Lee at al. (US-20230402454-A1; Lee2).
Regarding claim 7, Lee in view of Sun discloses the semiconductor memory device of claim 1, but is silent on wherein the semiconductor memory device comprises a plurality of first element isolation structures and a plurality of first element isolation patterns (material within the isolation structures), the plurality of first element isolation structures having different widths from each other, and the plurality of first element isolation patterns having different widths from each other.
The claim is worded such that the plurality of first element isolation structures and a plurality of first element isolation patterns are not the same as those claimed in claim 1.
Lee2 discloses a semiconductor device comprising a plurality of first element isolation regions (Fig.1A, 156/154 ¶42) having different widths and a plurality of element isolation patterns (Fig.1A, 155/153 ¶42) having different widths.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use the isolation configuration of Lee2 reduce variations in threshold voltages.
Allowable Subject Matter
Claims 6,10,15-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 18 is objected to due to its dependence on claim 17.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The relevant art (US-20220085048-A1, US-20230178595-A1, US-20230402454-A1) discloses a semiconductor device comprising a cell formed over a peripheral substrate wherein the peripheral substrate comprises a plurality of isolation structures defining a plurality of active regions, where a second isolation structure is deeper than a first isolation structure and a third isolation structure comprises first and second isolation patterns. The art is silent on the limitations cited below in combination with the rest of the claimed limitations.
Regarding claim 6, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein a width of the second element isolation structure is equal to a width of the second element isolation pattern.”, as recited in Claim 6, with the remaining features.
Regarding claim 15, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " a plurality of first element isolation patterns and a plurality of second element isolation patterns, the plurality of first element isolation patterns having different widths from each other, and wherein the plurality of second element isolation patterns have the same width.”, as recited in Claim 15, with the remaining features.
Regarding claim 16, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein a void is in … at least a part of the first element isolation pattern, and wherein a seam is in at least a part of the second element isolation structure and at least a part of the second element isolation pattern.”, as recited in Claim 16, with the remaining features.
Regarding claim 17, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein a width of the second element isolation structure is equal to a width of the second element isolation pattern.”, as recited in Claim 17, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 19, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the second width of the second element isolation structure is the same as
the fourth width of the second element isolation pattern, and”, as recited in Claim 19, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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