DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. REJECTIONS BASED ON DOUBLE PATENTING
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No.12,034,256. Although the claims at issue are not identical, they are not patentable distinct from each other, because the limitations of the circuitry described in claim 1 of the instant application (18/732,874) are taught/suggested in claim 2 of the patented application (U.S. Patent No.12,034,256) (Please note that as both the instant and patented applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and patented applications for the instant double patenting rejection)
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub.: 2021/0305805) in view of Terlizzi et al. (US Patent 7,863,906).
As per claim 1, Kim teaches/suggests a circuitry, comprising: one or more circuits (e.g. associated with circuitry in electronic device (101) in Fig. 2: [0049]-[0050]); a connector portion (e.g. associated with connector: [0054]-[0056]) coupled to the one or more circuits and comprising a plurality of pins (Fig. 2-3B; [0049]-[0061]); wherein, when the connector portion is coupled with a first connector in a first orientation; and wherein, when the connector portion is coupled with the first connector in a second orientation, the second orientation being different from the first orientation, at least one pin of the plurality of pins operating accordingly ([0055]) (Fig. 2-3B; and [0049]-[0061]).
Kim does not teach the circuitry, comprising:
the one or more circuits are configured to operate in a first state; and
receives a signal causing the one or more circuits to operate in a second state different from the first state.
Terlizzi teaches/suggests a circuitry, comprising: the one or more circuits are configured to operate in a first state (e.g. associated with operating one of USB standard, serial standard or unsupported: Fig. 8); and receives a signal causing the one or more circuits to operate in a second state different from the first state (e.g. associated with operating in another one of USB standard, serial standard or unsupported: Fig. 8) (Fig. 6-8; col. 2, ll. 9-33; and col. 8, l. 37 to col. 10, l. 46).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Terlizzi’s different states into Kim’s circuit operation for the benefit of a single connector to communicate with multiple type of devices (Kim, col. 2, ll. 19-23) to obtain the invention as specified in claim 1.
As per claim 2, Kim and Terlizzi teach/suggest all the claimed features of claim 1 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein the connector portion corresponds to specifications of a standardized connector including a plurality of pins with respectively assigned potentials (e.g. associated with having respectively assigned potentials in accordance to interconnecting protocol/standard) (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 3, Kim and Terlizzi teach/suggest all the claimed features of claim 2 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein the connector portion corresponds to a Universal Serial Bus Type C connector (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 4, Kim and Terlizzi teach/suggest all the claimed features of claim 2 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein the at least a first pin of the plurality of pins comprises a pin assigned to ground (GND) of the standardized connector (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 5, Kim and Terlizzi teach/suggest all the claimed features of claim 1 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein the connector portion is rotationally symmetric (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 6, Kim and Terlizzi teach/suggest all the claimed features of claim 1 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein a mechanism is configured to bring the one or more circuits into the second state by bringing the one or more circuits to a high impedance pin state (Kim, Fig. 2-3B; [0049]-[0061]; [0065]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 7, Kim and Terlizzi teach/suggest all the claimed features of claim 1 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein the signal is at ground potential (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 8, Kim and Terlizzi teach/suggest all the claimed features of claim 1 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein the one or more circuits detect either the first orientation or the second orientation from a digital signal (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 9, Kim and Terlizzi teach/suggest all the claimed features of claim 1 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein in case the connector portion is coupled with a connector incompatible with the connector portion, at least one first pin of the plurality of pins receives a reference potential that brings the one or more circuits into the second state (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 10, Kim and Terlizzi teach/suggest all the claimed features of claim 1 above, where Kim and Terlizzi further teach/suggest the circuitry comprising wherein the circuitry comprises a circuit board (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46), wherein it would have been obvious/well-known to one of ordinary skilled in the art to use integrate circuit on the circuit board.
As per claim 11, claim 11 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1.
As per claims 12-16, claims 12-16 are rejected in accordance to the same rational and reasoning as the above rejection of claims 2-6.
As per claim 17, Kim and Terlizzi teach/suggest all the claimed features of claim 11 above, where Kim and Terlizzi further teach/suggest the method comprising wherein the plurality of pins corresponds to specifications of a standardized connector (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 18, Kim and Terlizzi teach/suggest all the claimed features of claim 11 above, where Kim and Terlizzi further teach/suggest the method comprising wherein coupling the connector to the connector portion comprises coupling a connector that is incompatible with the connector portion (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 19, Kim and Terlizzi teach/suggest all the claimed features of claim 11 above, where Kim and Terlizzi further teach/suggest the method comprising wherein coupling the connector to the connector portion comprises coupling the connector in an incorrect orientation with the connector portion (Kim, Fig. 2-3B; [0049]-[0061]; and Terlizzi, Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
As per claim 20, Kim teaches/suggests an electrical connector, comprising: a plurality of pins arranged symmetrically, the plurality of pins containing a first pin and a second pin, and wherein the second pin is mirrored across a symmetric axis from the first pin (Fig. 3A-3B; [0053]-[0061]); and a mechanical interface that connects the plurality of pins to a circuit, wherein the mechanical interface can connect the plurality of pins to the circuit in a first orientation and a second orientation, wherein the first orientation and the second orientation are different (Fig. 2-3B: [0053]-[0055]); wherein when the electrical connector is coupled to the circuit through the mechanical interface in the first orientation (Fig. 2-3B; [0054]-[0055]); and wherein when the electrical connector is coupled to the circuit through the mechanical interface in the second orientation (Fig. 2-3B; [0054]-[0055]) (Fig. 2-3B; and [0049]-[0061]).
Kim does not teach the electrical connector comprising:
the circuit is configured to operate in a first state based on a first signal from the first pin; and
the circuit is configured to operate in a second state based on a second signal from the second pin
Terlizzi teaches/suggests an electrical connector comprising: the circuit is configured to operate in a first state based on a first signal from the first pin (e.g. associated with operating one of USB standard, serial standard or unsupported: Fig. 8); and the circuit is configured to operate in a second state based on a second signal from the second pin (e.g. associated with operating in another one of USB standard, serial standard or unsupported: Fig. 8) (Fig. 6-8; col. 2, ll. 9-33; col. 8, l. 37 to col. 10, l. 46).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Terlizzi’s different states into Kim’s circuit operation for the benefit of a single connector to communicate with multiple type of devices (Kim, col. 2, ll. 19-23) to obtain the invention as specified in claim 1.
III. CLOSING COMMENTS
\CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 January 30, 2026