PDSOI TRANSISTOR AND METHOD FOR FABRICATING SAME

Application No. 18/732,960

• Filed: Jun 04, 2024
• Priority: May 24, 2024 — CN 202410651280.6
• Examiner: PROSTOR, ANDREW VICTOR
• Assignee: Hangzhou Hfc Semiconductor Co.
• OA Round: 1 (Non-Final)

Office Action

Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Status of Claims
Claims 1-10 are pending.

Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "190" and "112" have both been used to designate the TiN layer in Fig. 5 of the instant application, it appears that the second instance of “190” was included by mistake. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.

Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.

Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0248013 A1 Chowdhury et al (herein “Chowdhury”).
Regarding Claim 1, Chowdhury discloses:
A partially depleted silicon-on-insulator (PDSOI) transistor (see generally the cross-section view of the generic embodiment of the SOI device shown in Fig. 14 unless otherwise stated), comprising:
a silicon-on-insulator (SOI) substrate (#30, includes semiconductor substrate #30 shown in Fig. 14 and underlying buried oxide layer (unlabeled) and underlying handle substrate (unlabeled), see [0041]: “…In one embodiment, the semiconductor substrate 30 can be a bulk semiconductor substrate consisting of a semiconductor material (e.g., single crystal silicon wafer), or can be a semiconductor-on-insulator (SOI) substrate including a buried insulator layer (such as a silicon oxide layer) underlying the semiconductor (e.g., silicon) material portion, and a handle substrate underlying the buried insulator layer.”), wherein the SOI substrate (#30) comprises a bottom silicon layer (unlabeled, see [0041]), a buried oxide layer (unlabeled, see [0041]) formed on the bottom silicon layer and a top silicon layer (#30) formed on the buried oxide layer;
a gate structure (see annotated Fig. 14 below, includes #52, #54, and #56) formed on the SOI substrate (#30);
a source (#34S, [0078]) and a drain (#34D, [0078]) formed in the top silicon layer (#30) on opposite sides of the gate structure (#52, #54, and #56), wherein a first space (see annotated Fig. 14 below) is provided between a bottom surface of the source (#34S) and a top surface of the buried oxide layer (unlabeled, see [0041]) and wherein a second space (see annotated Fig. 14 below) is provided between a bottom surface of the drain (see annotated Fig. 14 below) and the top surface of the buried oxide layer (unlabeled, see [0041]); and
a source contact structure (#88S) and a drain contact structure (#88D), wherein the source contact structure (#88S) is connected to the source (#34S), wherein the drain contact structure (#88D) is connected to the drain (#34D), and wherein the source contact structure (#88S) extends into the source (#34S) and a third space (see annotated Fig. 14 below) is provided between the source contact structure (#88S) and the top surface of the buried oxide layer (unlabeled, see [0041]).

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Chowdhury Fig. 14 – Annotated by Examiner

Regarding Claim 2, Chowdhury discloses: The PDSOI transistor of claim 1,
Chowdhury further discloses:
wherein the third space (see annotated Fig. 14 above) contains doping ions ([0078]-[0079]).

Regarding Claim 3, Chowdhury discloses: The PDSOI transistor of claim 2,
Chowdhury further discloses:
wherein the PDSOI transistor is an NMOS device, and the doping ions are boron ions; or
wherein the PDSOI transistor is a PMOS device, and wherein the doping ions are phosphorus ions ([0072]-[0079]).

Regarding Claim 4, Chowdhury discloses: The PDSOI transistor of claim 1,
Chowdhury further discloses:
wherein the third space includes the first space (see annotated Fig. 14 above).

Regarding Claim 5, Chowdhury discloses: The PDSOI transistor of claim 4,
Chowdhury further discloses:
wherein the third space further includes a portion of the source (#34S) between the source contact structure (#32S) and the first space ([0073]-[0074], [0078], both the source and the source extension region (and respective drain regions) have overlapping concentrations of the same conductivity type doping ions, therefore the third space that comprises doping ions may be considered a portion of both regions which reads on the claimed limitation).

Regarding Claim 6, Chowdhury discloses: The PDSOI transistor of claim 1,
Chowdhury further discloses:
wherein each of the first space (see annotated Fig. 14 above) and the second space (see annotated Fig. 14 above) has a dimension greater than 5 nm in a thickness direction of the SOI substrate ([0043]: “…the thickness of the top semiconductor material layer within the semiconductor substrate 30 may be in a range from 100 nm to 1,000 nm”, see Fig. 14).

Regarding Claim 7, Chowdhury discloses: The PDSOI transistor of claim 1,
Chowdhury further discloses:
wherein the third space has a dimension ranging from 5 nm to 15 nm in a thickness direction of the SOI substrate ([0043]: “…the thickness of the top semiconductor material layer within the semiconductor substrate 30 may be in a range from 100 nm to 1,000 nm”, see Fig. 14).

Regarding Claim 8, Chowdhury discloses:
A method for fabricating a partially depleted silicon-on-insulator (PDSOI) transistor (see generally the cross-section view of the generic embodiment of the SOI device shown in Fig. 14 unless otherwise stated), comprising:
providing a silicon-on-insulator (SOI) substrate (#30, includes semiconductor substrate #30 shown in Fig. 14 and underlying buried oxide layer (unlabeled) and underlying handle substrate (unlabeled), see [0041]: “…In one embodiment, the semiconductor substrate 30 can be a bulk semiconductor substrate consisting of a semiconductor material (e.g., single crystal silicon wafer), or can be a semiconductor-on-insulator (SOI) substrate including a buried insulator layer (such as a silicon oxide layer) underlying the semiconductor (e.g., silicon) material portion, and a handle substrate underlying the buried insulator layer.”), wherein the SOI substrate (#30) comprises a bottom silicon layer (unlabeled, see [0041]), a buried oxide layer (unlabeled, see [0041]) formed on the bottom silicon layer (unlabeled, see [0041]) and a top silicon layer (#30) formed on the buried oxide layer (unlabeled, see [0041]);
forming a gate structure (see annotated Fig. 14 below, includes #52, #54, and #56) on the SOI substrate (#30);
forming a source (#34S, [0078]) and a drain (#34D, [0078]) in the SOI substrate (#30), wherein the source (#34S) and the drain (#34D) are formed in the top silicon layer (#30) on opposite sides of the gate structure (#52, #54, and #56), wherein a first space (see annotated Fig. 14 below) is provided between a bottom surface of the source (#34S) and a top surface of the buried oxide layer (unlabeled, see annotated Fig. 14 below), and wherein a second space (see annotated Fig. 14 below) is provided between a bottom surface of the drain (#34D) and the top surface of the buried oxide layer (unlabeled, see annotated Fig. 14 below);
forming an interlayer dielectric layer (#74, [0081]-[0083]) on the SOI substrate (#30), wherein the interlayer dielectric layer (#74) covers each of the gate structure (#52, #54, #56) and the SOI substrate (#30); and
forming a source contact structure (#88S) and a drain contact structure (#88D) in the interlayer dielectric layer (#74), wherein the source contact structure (#88S) is connected to the source (#34S), wherein the drain contact structure (#88D) is connected to the drain (#34D), and wherein the source contact structure (#88D) extends into the source (#34S) and a third space (see annotated Fig. 14 below) is provided between the source contact structure (#88S) and the top surface of the buried oxide layer (unlabeled, see annotated Fig. 14 below).

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Chowdhury Fig. 14 – Annotated by Examiner

Allowable Subject Matter
Claims 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 9: The following is a statement of reasons for the indication of allowable subject matter: The prior art of record as considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations. The prior art fails to teach or suggest the claimed limitations, namely: “performing an ion implantation process on the third space through the first opening so that the third space contains doping ions;”
Regarding Claim 10: Claim 10 is dependent on objected to but allowable claim 9, and is also objected to but allowable for at least the same reasons as claim 9.

Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is [phone]. The examiner can normally be reached M-F 8:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812

Prosecution Timeline

• Jun 04, 2024: Application Filed
• Jul 29, 2026: Non-Final Rejection mailed — §102 (current)