DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 11-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maejima (US 2021/0125660) in view of Park et al. (US 2022/0157754 ‒hereinafter Park), and further in view of Sakui (US 9,679,650).
Regarding claim 1, Maejima discloses a memory device, comprising:
a first chip (memory chip MC; fig. 7) including a first memory cell array (“memory region MR includes a plurality of NAND strings NS [of a first memory cell array 10a]” fig. 2, 7 para 0107);
including a second memory cell array (10b; fig. 2); and
a third chip (CMOS chip CC; fig. 7) including a control circuit (“circuit unit [i.e. of CMOS chip CC] further includes a controller” claim 9) and in contact (i.e. bonded) with the second chip (“circuit unit bonded to the memory unit [i.e. of memory chip MC]” para 0045),
wherein
the first memory cell array (10a) includes a first transistor (ST1/MT of any block BLK0-BLK7; fig. 2, 3) and a second transistor (another memory transistor MT of any block BLK0-BLK7; fig. 2, 3) coupled in series (para 0070),
the second memory cell array (10b) includes a third transistor (ST1 of any block BLK8-BLK15; fig. 2, 3) and a fourth transistor (memory transistor MT of any block BLK8-BLK15; fig. 2, 3) coupled in series (para 0070), and
the control circuit (i.e. the controller) includes:
a fifth transistor having a first end electrically coupled to a gate of the first transistor (any transistor TR9-TR12/TR1-TR8, of row decoder RD0-RD7, having a first end electrically coupled to a gate of ST1/MT via respective line SGD0-SGD3/WL0-WL7, of array 10a; fig. 2, 3, 6);
a sixth transistor having a first end electrically coupled to a gate of the third transistor (any transistor TR9-TR12 of row decoder RD8-RD15 having a first end electrically coupled to a gate of ST1 via respective line SGD0-SGD3, of array 10b; fig. 2, 3, 6);
a first decoder (i.e. RD0; fig. 6) configured to switch a state (“L” or “H”; para 0101) of the fifth transistor (any transistor TR9-TR12 of RD0); and
a second decoder (i.e. RD8; fig. 6) configured to switch a state (“L” or “H”; para 0101) of the sixth transistor (any transistor TR9-TR12 of RD8) independently of the state of the fifth transistor (switching via block decoder BD of the first decoder RD0 is independent of switching via block decoder BD of the second decoder RD8; fig. 6).
Maejima does not expressly disclose a second chip including a second memory cell array and in contact with the first chip; a seventh transistor having a first end electrically coupled to a gate of the second transistor and a gate of the fourth transistor.
Park discloses a second chip (upper chip including cell region CELL2; fig. 18) including a second memory cell array (CELL2) and in contact (i.e. bonded; para 0137) with the first chip (upper chip including cell region CELL1; fig. 18).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima (having a first and second memory array) is modifiable as taught by Park (having a first chip including a first memory array and a second chip including a second memory array) for the purpose of achieving a reduction in size by vertical stacking of the memory in a highly integrated device (para 0003, 0138 of Park).
Sakui discloses a seventh transistor (940 of driver 938; fig. 8) having a first end electrically coupled to a gate of the second transistor (CD15 of first array 908; fig. 9) and a gate of the fourth transistor (CD15 of second array 906; fig. 9).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima having a driver is further modifiable as taught by the driver of Sakui, for the purpose of selectively driving required voltages to facilitate data accessing schemes in a highly integrated device having increased number of memory arrays (column/line(s): 12/41-56 of Sakui).
Regarding claim 11, Maejima discloses the memory device, wherein the first transistor is a select transistor (select transistor ST1; fig. 3), and the second transistor is a memory cell transistor (memory transistor MT; fig. 3).
Regarding claim 12, Maejima discloses the memory device, wherein the first transistor and the second transistor are memory cell transistors (i.e. memory transistor MT and another memory transistor MT; fig. 3).
Regarding claim 13, Maejima discloses the memory device, wherein the first chip, the and the third chip are arranged in a first direction (Z direction; fig. 15), the first memory cell array includes: a first conductor layer (31/33; fig. 15) and a second conductor layer (32; fig. 15), each of the first conductor layer and the second conductor layer extending in a plane (X plane; fig. 15) intersecting with the first direction and provided apart from each other in the first direction; and a first member (MP; fig. 15) extending in the first direction and having a first portion (first end portion; fig. 15) intersecting with the first conductor layer to function as the first transistor and a second portion (another end portion; fig. 15) intersecting with the second conductor layer to function as the second transistor, and the first portion is located at an end portion of the first member with respect to the second portion in the first direction (fig. 15).
Maejima does not expressly disclose the second chip.
Park discloses the second chip (fig. 18).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima (having a first and second memory array) is modifiable as taught by Park (having a first chip including a first memory array and a second chip including a second memory array) for the purpose of achieving a reduction in size by vertical stacking of the memory in a highly integrated device (para 0003, 0138 of Park).
Regarding claim 14, Maejima discloses the memory device, wherein the first chip, the and the third chip are arranged in a first direction (Z direction; fig. 15), the first memory cell array includes: a first conductor layer (31/33; fig. 15) and a second conductor layer (32; fig. 15), each of the first conductor layer and the second conductor layer extending in a plane (X plane; fig. 15) intersecting with the first direction and provided apart from each other in the first direction; and a first member (MP; fig. 15) extending in the first direction and having a first portion (first end portion; fig. 15) intersecting with the first conductor layer to function as the first transistor and a second portion (another end portion; fig. 15) intersecting with the second conductor layer to function as the second transistor, and the first portion is located at an end portion of the first member with respect to the second portion in the first direction (fig. 15).
Maejima does not expressly disclose the second chip.
Park discloses the second chip (fig. 18).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima (having a first and second memory array) is modifiable as taught by Park (having a first chip including a first memory array and a second chip including a second memory array) for the purpose of achieving a reduction in size by vertical stacking of the memory in a highly integrated device (para 0003, 0138 of Park).
Regarding claim 15, Maejima discloses the memory device, wherein the first chip, the and the third chip are arranged in a first direction (Z direction; fig. 15), the first memory cell array includes: a first conductor layer (31/33; fig. 15) and a second conductor layer (32; fig. 15), each of the first conductor layer and the second conductor layer extending in a plane (X plane; fig. 15) intersecting with the first direction and provided apart from each other in the first direction; and a first member (MP; fig. 15) extending in the first direction and having a first portion (first end portion; fig. 15) intersecting with the first conductor layer to function as the first transistor and a second portion (another end portion; fig. 15) intersecting with the second conductor layer to function as the second transistor, the first member includes: a first sub-member (43; fig. 10) including the first portion; and a second sub-member (42; fig. 10) in contact with the first sub-member in the first direction, a side surface (outer side surface; fig. 10) of the first sub-member is shifted from an extension of a side surface (inner/outer side surface; fig. 10) of the second sub-member, and the first portion is located at an end of the first sub-member with respect to the second portion in the first direction (fig. 10).
Maejima does not expressly disclose the second chip.
Park discloses the second chip (fig. 18).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima (having a first and second memory array) is modifiable as taught by Park (having a first chip including a first memory array and a second chip including a second memory array) for the purpose of achieving a reduction in size by vertical stacking of the memory in a highly integrated device (para 0003, 0138 of Park).
Regarding claim 16, Maejima discloses the memory device, wherein the first chip, the and the third chip are arranged in a first direction (Z direction; fig. 15), the first memory cell array includes: a first conductor layer (31/33; fig. 15) and a second conductor layer (32; fig. 15), each of the first conductor layer and the second conductor layer extending in a plane (X plane; fig. 15) intersecting with the first direction and provided apart from each other in the first direction; and a first member (MP; fig. 15) extending in the first direction and having a first portion (first end portion; fig. 15) intersecting with the first conductor layer to function as the first transistor and a second portion (another end portion; fig. 15) intersecting with the second conductor layer to function as the second transistor, the first member includes: a first sub-member (43; fig. 10) including the first portion; and a second sub-member (42; fig. 10) in contact with the first sub-member in the first direction, a side surface (outer side surface; fig. 10) of the first sub-member is shifted from an extension of a side surface (inner/outer side surface; fig. 10) of the second sub-member, and the first portion is located at an end of the first sub-member with respect to the second portion in the first direction (fig. 10).
Maejima does not expressly disclose the second chip.
Park discloses the second chip (fig. 18).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima (having a first and second memory array) is modifiable as taught by Park (having a first chip including a first memory array and a second chip including a second memory array) for the purpose of achieving a reduction in size by vertical stacking of the memory in a highly integrated device (para 0003, 0138 of Park).
Regarding claim 17, Maejima discloses a memory device, comprising:
a first chip (memory chip MC; fig. 7) including a first memory cell array (“memory region MR includes a plurality of NAND strings NS [of a first memory cell array 10a]” fig. 2, 7 para 0107);
including a second memory cell array (10b; fig. 2); and
a third chip (CMOS chip CC; fig. 7) including a control circuit (“circuit unit [i.e. of CMOS chip CC] further includes a controller” claim 9) and in contact (i.e. bonded) with the second chip (“circuit unit bonded to the memory unit [i.e. of memory chip MC]” para 0045),
wherein
the first memory cell array (10a) includes a first transistor (ST1/MT of any block BLK0-BLK7; fig. 2, 3) and a second transistor (memory transistor MT of any block BLK0-BLK7; fig. 2, 3) coupled in series (para 0070),
the second memory cell array (10b) includes a third transistor (ST1 of any block BLK8-BLK15; fig. 2, 3) and a fourth transistor (memory transistor MT of any block BLK8-BLK15; fig. 2, 3) coupled in series (para 0070), and
the control circuit (i.e. the controller) includes:
a fifth transistor having a first end electrically coupled to a gate of the first transistor (any transistor TR9-TR12/TR1-TR8, of row decoder RD0-RD7, having a first end electrically coupled to a gate of ST1/MT via respective line SGD0-SGD3/WL0-WL7, of array 10a; fig. 2, 3, 6);
a sixth transistor having a first end electrically coupled to a gate of the third transistor (any transistor TR9-TR12 of row decoder RD8-RD15 having a first end electrically coupled to a gate of ST1 via respective line SGD0-SGD3, of array 10b; fig. 2, 3, 6); and
a decoder (decoder module 16; fig. 6) configured to switch (“L” or “H”; para 0101) of the fifth transistor (any transistor TR9-TR12 of RD0) and (“L” or “H”; para 0101) of the sixth transistor (any transistor TR9-TR12 of RD8) independently (switching via block decoder BD of RD0 is independent of switching via block decoder BD of RD8; fig. 6).
Maejima does not expressly disclose a second chip including a second memory cell array and in contact with the first chip; a seventh transistor having a first end electrically coupled to a gate of the second transistor and a gate of the fourth transistor.
Park discloses a second chip (upper chip including cell region CELL2; fig. 18) including a second memory cell array (CELL2) and in contact (i.e. bonded; para 0137) with the first chip (upper chip including cell region CELL1; fig. 18).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima (having a first and second memory array) is modifiable as taught by Park (having a first chip including a first memory array and a second chip including a second memory array) for the purpose of achieving a reduction in size by vertical stacking of the memory in a highly integrated device (para 0003, 0138 of Park).
Sakui discloses a seventh transistor (940 of driver 938; fig. 8) having a first end electrically coupled to a gate of the second transistor (CD15 of first array 908; fig. 9) and a gate of the fourth transistor (CD15 of second array 906; fig. 9).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima having a driver is further modifiable as taught by the driver of Sakui, for the purpose of selectively driving required voltages to facilitate data accessing schemes in a highly integrated device having increased number of memory arrays (column/line(s): 12/41-56 of Sakui).
Regarding claim 18, Maejima discloses the memory device, wherein each of the first memory cell array and the second memory cell array includes a plurality of partial blocks (fig. 3), and a first partial block (NS of array 10a; fig. 3) among the plurality of partial blocks included in the first memory cell array includes the first transistor and the second transistor, a second partial block among (NS of array 10b; fig. 2, 3) the plurality of partial blocks included in the second memory cell array includes the third transistor and the fourth transistor, a set including the first partial block and the second partial block is a unit of erasing data (para 0051), and the decoder (16; fig. 2) corresponds to the set including the first partial block and the second partial block.
Regarding claim 19, Maejima discloses the memory device, wherein the decoder includes: a first decoder (any of RD0-RD7; fig. 2, 6) corresponding to the first partial block and configured to switch the state of the fifth transistor; and a second decoder (any of RD8-RD15; fig. 2, 6) corresponding to the second partial block and configured to switch the state of the sixth transistor independently of the state of the fifth transistor (switching via block decoder BD of the first decoder is independent of switching via block decoder BD of the second decoder; fig. 6).
Allowable Subject Matter
Claim(s) 2-10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 2 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely control circuit further includes a third decoder, and the third decoder is configured to: turn on a state of the seventh transistor in a case where the state of the fifth transistor is turned on or in a case where the state of the sixth transistor is turned on; and turn off the state of the seventh transistor in a case where the state of the fifth transistor is turned off and the state of the sixth transistor is turned off.
The allowable claims are supported in at least fig. 3 of the instant application.
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824