Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/733,057 filed June 4, 2024. Claims 1-18 are currently pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7, 10-13 & 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (Chinese Publication 106952954) in view of Nieh (Pre-Grant Publication 2012/0108026).
Regarding claim 1, Chen discloses a transistor device comprising:
a silicon-on-insulator (SOI) substrate (Fig. 5f) comprising a bottom silicon layer (204), a buried oxide layer (205) formed on the bottom silicon layer and a top silicon layer (207) formed on the buried oxide layer, wherein a well region (207) is formed in the top silicon layer;
a gate structure (201) formed on the SOI substrate; and
a source and a drain (202 & 203), wherein the source and the drain are located in the well region on opposite sides of the gate structure, and wherein at least a portion of the source has a same conductivity type (P-type) as the P-type well region.
Chen does not disclose the source is formed by epitaxy. However Nieh discloses a transistor device comprising:
Forming a source/drain region (Fig. 7, 252) of a transistor by epitaxy (Paragraph [0025]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the source by an epitaxy process because of the epitaxial grown source/drain region will have enhanced carrier mobility and improve device performance (Paragraph [0003]).
Regarding claim 2, Chen further discloses:
the source comprises a primary source (2022), wherein the primary source has a same conductivity type as the well region, and wherein the primary source has a higher dopant concentration (P+) than the well region (P).
Regarding claim 3, Chen further discloses:
the source further comprises a secondary source (2021), wherein the primary source and the secondary source are located side by side along an extending direction of the SOI substrate, and wherein the secondary source has a conductivity type (N+) different from a conductive type of the well region (P).
Regarding claim 7, Chen further discloses:
a lightly doped source region (2023) and a lightly doped drain region (2023), wherein each of the lightly doped source region and the lightly doped drain region extends from the well region under the gate structure to the well region beside the gate structure.
Regarding claim 10, & 12-13, Chen disclose a transistor device comprising:
providing a silicon-on-insulator (SOI) substrate (Fig. 5a-5g), wherein the SOI substrate comprises a bottom silicon layer (204), a buried oxide layer (205)formed on the bottom silicon layer and a top silicon layer (207) formed on the buried oxide layer, and wherein at least one well region (207) is formed in the top silicon layer;
forming at least one gate structure (201) on the SOI substrate; and
forming at least one source (202) and at least one drain (203) in the SOI substrate, wherein the source and the drain are located in the well region on opposite sides of the gate structure, and wherein at least a portion of the source is of a same conductivity type (P-type) as the p-type well region.
Chen does not disclose the source is formed by epitaxy. However Nieh discloses a transistor device comprising:
Forming a source/drain region (Fig. 7, 252) of a transistor by forming an opening (Fig. 6a, 250) in the SOI (Paragraph [0009]) by etching the substrate with a patterned photoresist/mask (248) and epitaxally growning the source/drain (252) in the opening (Paragraph [0025]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the source by an epitaxy process because of the epitaxial grown source/drain region will have enhanced carrier mobility and improve device performance (Paragraph [0003]).
Regarding claim 11, Chen further discloses:
performing an ion implantation process on the at least one well region to form at least one lightly doped source region (Fig. 5c, 2023) and at least one lightly doped drain region (2023)(Paragraph [0092]).
Regarding claim 17, Chen further discloses:
the source comprises a primary source, wherein the primary source (2022) has a same conductivity type as the well region, and wherein the primary source has a higher dopant concentration (P+) than the well region (P).
Regarding claim 18, Chen further discloses:
the source further comprises a secondary source (2021), wherein the primary source and the secondary source are located side by side along an extending direction of the SOI substrate, and wherein the secondary source has a conductivity type (N) different from a conductive type of the well region (P).
Claim(s) 6, 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (Chinese Publication 106952954) in view of Nieh (Pre-Grant Publication 2012/0108026) as applied to claim 1, 2 & 7 above, and further in view of Ono (Pre-Grant Publication 2022/0109070).
Regarding claim 6, 8, 9, Chen and Nieh disclose all of the limitations of claim 1, 2 & 7 above. Neither reference disclose the source contains ions at a concentration greater than or equal to 1.0e20cm⁻3, each of the lightly doped source region and the lightly doped drain region is greater than or equal to 1.0e15cm⁻3, or an interlayer dielectric layer covering each of the SOI substrate and the gate structure; and a gate contact, a source contact and a drain contact formed in the interlayer dielectric layer, wherein: the gate contact is connected to the gate structure; the source contact is connected to the source; and the drain contact is connected to the drain. However Ono discloses a transistor device comprising:
A source /drain region (Fig. 7b, 234s/234d) having an ion concentration of 5.0×1018cm3 – 2.0×1021cm3 (Paragraph [0106]), a lightly doped source/drain (232s/232d) having a concentration of 1.0×1018cm3 – 1.0×1019cm3 (Paragraph [0100]).
Ono further discloses a gate contact (88g), source contact (88s), and drain contact (88d) extending through an interlayer dielectric (70) coupled to the gate, source, and drain.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the source/drain region having an ion concentration of 5.0×1018cm3 – 2.0×1021cm3 and the lightly doped source/drain (232s/232d) having a concentration of 1.0×1018cm3 – 1.0×1019cm3 because it will serve to improve the breakdown characteristic of the transistor allowing for higher voltage operations (Paragraph [0073 & 0212]). Further the metal contacts coupled to the source, gate, and drain will serve to provide an current path to the source region, gate electrode, and drain region.
Allowable Subject Matter
Claims 4-5 & 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 is considered allowable because none of the prior art either alone or in combination discloses: the secondary source is closer to the gate structure than the primary source.
Claim 5 is considered allowable because none of the prior art either alone or in combination discloses a first side of the primary source is spaced at a first distance from a second side of the primary source, wherein a first side of the primary source is spaced at a second distance from a third side of the gate structure, wherein the first distance is less than or equal to 0.5 times the second distance, and wherein: the first side is a side of the primary source far away from the gate structure; the second side is a side of the primary source proximal to the gate structure; and the third side is a side of the gate structure proximal to the source.
Claim 14 is considered allowable because none of the prior art either alone or in combination discloses forming at least one second opening in the SOI by etching at least the SOI substrate with a second patterned mask layer serving as a mask. Claim 15-16 are also allowable based on their dependency from claim 14.
Conclusion
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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