DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/11/2025 and 06/04/2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Pg. 7, ¶ [0033], line 3, “and” in “substrate 110 through and the front-side…” should be omitted.
Pg. 15, ¶ [0052], lines 2-3 bottom up, ““Vout_2” shows a smaller amplitude than that of the condition “Vout_2””. The second “Vout_2” should be “Vout_1.”
Pg. 16, ◙ [0055], line 3 from top of page 16, “PM2 is can be”, “is” should be omitted.
Pg. 18, ¶ [0061], line 4 bottom up, “300and together” should be “300 together.”
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1, line 12, “etching an first” should be “etching a first”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-9, 13-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 6 and 13 recite “depositing a second high-k dielectric layer over the second high-k dielectric layer” is indefinite as layer cannot be deposited over itself. As shown in Figs. 12-17 and ¶¶ [0042-0049] of the spec, a second high-k layer is deposited over the first high-k layer. The limitation is thus best understood as “depositing a second high-k dielectric layer over the first high-k dielectric layer”. Claims 7-9, and 14 depend on claims 6 and 13 respectively, and are indefinite for same reasons.
Claim 7 recites, “depositing a metal material over the second high-k dielectric layer and into second opening in the second high-k dielectric layer”. As best understood by the examiner, first instance of “second high-k dielectric layer” is referencing second high-k dielectric layer and second instance of “second high-k dielectric layer” is referencing second high-k dielectric layer.
Claim 14 recites, “wherein the thermal conductivity of the second high-k dielectric layer is greater than a thermal conductivity of the frontside dielectric layer”. As best understood by the examiner, the “second high-k dielectric layer” is referencing second high-k dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 15-16, 18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20220359375 A1)
Regarding claim 1, Huang discloses A method ([0010]) for fabricating an integrated circuit structure, comprising:
forming a semiconductor device (Fig. 1) over a semiconductor substrate (50, Fig. 1), wherein the semiconductor device comprises a gate structure (102, Fig. 1) and first and second source/drain regions (92, Fig. 1) respectively on opposite sides of the gate structure;
forming a frontside interconnect structure (120, Figs. 21A-21C, ¶ [0066]) over a frontside (120, Fig. 22A) of the semiconductor device, wherein the frontside interconnect structure comprises a frontside metal line (112, Fig. 21C) and a frontside dielectric layer (106, Fig. 21C), and the frontside metal line is electrically connected to the first source/drain region of the semiconductor device;
depositing a first high-k dielectric layer (125, Figs. 24A-24C, ¶¶ [0079-0080]) over a backside (125, 129, 130, Fig. 24C) of the semiconductor device;
etching a first opening (128, Figs. 25A-C, ¶¶ [0080-0081]) in the first high-k dielectric layer to expose a backside (129, Fig.25C) of the second source/drain region; and
forming a first backside metal feature (130, Figs. 26A-C, ¶¶ [0082-0083]) in the first opening in the first high-k dielectric layer.
Huang does not disclose wherein a dielectric constant of the first high-k dielectric layer is greater than about 3.9; however, Huang discloses (¶ [0089]) the first dielectric layer has a dielectric constant between 2.6-40 or greater than 7.0); Artisans in the art would have selected a dielectric constant range greater than 3.9 out of the disclosed range of 2.6-40 or greater than 7 to yield reasonable results for optimal applications. As such it would have been obvious to one of ordinary skill in the art at before the effective filing date of the invention to select a dielectric constant range for the first high-k dielectric layer to be greater than 3.9 out of the range of 2.6-40 or greater than 7 to for optimal applications. Doing so would allow greater charge storage on capacitors, reducing leakage current and enhancing device performance.
Regarding claim 2, Huang discloses the method of claim 1. Huang does not disclose wherein the dielectric constant of the first high-k dielectric layer in a range from about 5 to about 10; however, Huang discloses (¶ [0089]) the first dielectric layer has a dielectric constant between 2.6-40 or greater than 7.0); Artisans in the art would have selected a dielectric constant range from 5 to 10 out of the range of 2.6-40 or greater than 7 to yield reasonable results for optimal applications. As such it would have been obvious to one of ordinary skill in the art at before the effective filing date of the invention to select a dielectric constant range for the first high-k dielectric layer to be in the range of 5-10 out of the range of 2-6-40 or greater than 7 to for optimal applications. Doing so would allow greater charge storage on capacitors, reducing leakage current and enhancing device performance.
Regarding claim 3, Huang discloses the method of claim 1. Though not disclosing the dielectric constant of the first high-k dielectric layer (125) is greater than a dielectric constant of the frontside dielectric layer (106), Huang discloses the two dielectric layers having the same dielectric constant. Absent unpredictable results, selecting the constant dielectric of the first high-k dielectric layer to be greater than that of the frontside dielectric layer can be achieved though routine optimization for a diversity of applications. MPEP 2144.05
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select the dielectric constant of the backside layer to be greater than that of the frontside layer for optimal applications. Doing so would allow for a diversity of optimal applications.
Regarding claim 4, Huang discloses the method of claim 1 and forming the first backside metal feature comprises depositing a metal material (130, into the first opening in the first high-k dielectric layer (130, Figs. 26A-C, ¶¶ [0082-0083]), but is silent regarding: depositing a metal material over the first high-k dielectric layer and into the first opening in the first high-k dielectric layer; and planarizing the metal material until the first high-k dielectric layer is exposed.
However, Huang discloses (¶ [0085]) a method of blanket deposition including depositing a blanket conductive film (134. Fig. 28F) over a via opening (patterning recesses on dielectric layer 132, Fig. 28F), using atomic layer deposition (ALD) or other suitable deposition technique, and planarizing the blanket film down to expose the top of the dielectric material (e.g. using CMP). Artisans in the art would have appreciated using blanket deposition can streamline processes as multiple deposition can be consolidated into one session.
As such one of ordinary skill in the art before the effective filing date of the invention would have adopted the blanket deposition of metal 134 over layer 132 for the deposition of 130 over layer 125 for time and cost saving. Doing so would streamline processes of production.
Regarding claim 5, Huang discloses the method of claim 4. Huang further discloses the method comprising:
depositing a metal barrier layer (129, ¶¶ [0081-0082]) into the first opening in the first high-k dielectric layer prior to depositing the metal material.
Regarding claim 6, Huang discloses the method of claim 1, further comprising: depositing a second high-k dielectric layer (132, Fig. 28F) over the first high-k dielectric layer (125
etching a second opening (patterning recesses in 132, ¶ [0085]) in the second high-k dielectric layer to expose the first backside metal feature; and forming a second backside metal feature (134) over the first backside metal feature.
Huang does not disclose wherein a dielectric constant of the second high-k dielectric layer is greater than about 3.9; however, Huang discloses (¶ [0089]) the first dielectric layer has a dielectric constant between 2.6-40 or greater than 7.0); Artisans in the art would have selected a dielectric constant range greater than 3.9 out of the disclosed range of 2.6-40 or greater than 7 to yield reasonable results for optimal applications. As such it would have been obvious to one of ordinary skill in the art at before the effective filing date of the invention to select a dielectric constant range for the second high-k dielectric layer to be greater than 3.9 out of the range of 2.6-40 or greater than 7 to for optimal applications. Doing so would allow greater charge storage on capacitors, reducing leakage current and enhancing device performance.
Regarding claim 7, Huang discloses the method of claim 6, and wherein forming the second backside metal feature comprises:
depositing a metal material (134, Fig. 28F) over the second high-k dielectric layer and into the second opening in the second high-k dielectric layer; and
planarizing the metal material until the second high-k dielectric layer is exposed (¶ [0085]).
Regarding claim 8, Huang discloses the method of claim 6 but is silent regarding the first and second high-k dielectric layers comprise different materials. However, Huang discloses the first and second layers may be comprised of the same material (¶ [0084]), thus one of ordinary skill in the art before the effective filing date of the invention would have selected different material for each layer for a diversity of applications.
Regarding claim 9, Huang discloses the method of claim 6, wherein the first and second high-k dielectric layers comprise a same material (¶ [0084]).
Regarding claim 15, Huang discloses An integrated circuit structure (Fig. 1), comprises:
a semiconductor device (Fig. 1) comprising a gate structure (102, Fig. 1) and first and second source/drain regions (92, Fig. 1) respectively on opposite sides of the gate structure;
a frontside metal line (112, Fig. 21C) over a frontside (¶ [0069]) of the semiconductor device and electrically connected to the first source/drain region of the semiconductor device;
a frontside dielectric layer (106, Fig. 21C) having a first dielectric constant (high-k material like 141, ¶¶ [0080, 0089]) and surrounding the frontside metal line;
a backside metal line (130, Fig. 26C) over a backside of the semiconductor device and electrically connected to the second source/drain region of the semiconductor device (¶ [0085]); and
a backside dielectric layer (125, Fig. 26C) having a second dielectric constant (high-k 141, ¶ [0089]) and surrounding the backside metal line.
Though disclosing the two layers may have the same dielectric material, Huang is silent regarding wherein the second dielectric constant is greater than the first dielectric constant.
Absent unpredictable results, selecting the constant dielectric of the first high-k dielectric layer to be greater than that of the frontside dielectric layer can be achieved though routine optimization. MPEP 2144.05
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select the dielectric constant of the backside layer to be greater than that of the frontside layer for optimal applications. Doing so would allow a variety of material selection for optimal applications.
Regarding claim 16, Huang discloses the integrated circuit structure of claim 15. Huang does not disclose wherein a dielectric constant of the second high-k dielectric layer is greater than about 3.9; however, Huang discloses (¶ [0089]) the first dielectric layer has a dielectric constant between 2.6-40 or greater than 7.0); Artisans in the art would have selected a dielectric constant range greater than 3.9 out of the disclosed range of 2.6-40 or greater than 7 to yield reasonable results for optimal applications. As such it would have been obvious to one of ordinary skill in the art at before the effective filing date of the invention to select a dielectric constant range for the second high-k dielectric layer to be greater than 3.9 out of the range of 2.6-40 or greater than 7 to for optimal applications. Doing so would allow greater charge storage on capacitors, reducing leakage current and enhancing device performance.
Regarding claim 18, Huang discloses the integrated circuit structure of claim 15. Though being silent regarding a thermal conductivity of the backside dielectric layer is greater than a thermal conductivity of the frontside dielectric layer., Huang discloses the front side dielectric and the backside dielectric are of the same material (¶ [0084]). It would be predictable for one of ordinary skill in the art to select two different dielectric layers for the frontside and the backside and the backside dielectric thermal conductivity is greater than that of the front size because the backside interconnects often comprise of power interconnection network. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select the backside dielectric thermal conductivity to be greater than that of the front side for optimal operations. Doing so would allow the backside to maintain material’s ability to maintain its physical and mechanical properties over long periods of exposure to high temperature induced by power components in the backside.
Regarding claim 20, Huang discloses the integrated circuit structure of claim 15. Though a height of the backside metal line appears to have the same height of the frontside metal line in Huang’s disclosure, it is predictable to have the backside height to be greater than the front side height as the backside interconnections often comprise backside power network. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to appreciate the backside height being greater than the front side height to reserve extra room for the respective power interconnections. Doing so would ensure adequate space to safely house electrical components in the backside.
Claim(s) 10-14, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20220359375 A1) in view of Wagner (US 20230103023 A1)
Regarding claim 10, Huang discloses A method for fabricating an integrated circuit structure (¶ [0010]), comprising:
forming a semiconductor device (Fig. 1) over a semiconductor substrate (50, Fig. 1), wherein the semiconductor device comprises a gate structure (102, Fig. 1) and first and second source/drain regions (92, Fig. 1) respectively on opposite sides of the gate structure;
forming a frontside interconnect structure (120, Figs. 21A-21C, ¶ [0066]) over a frontside (120, Fig. 21C) of the semiconductor device, wherein the frontside interconnect structure comprises a frontside metal line (112, Fig. 21C) and a frontside dielectric layer (106), and the frontside metal line is electrically connected to the first source/drain region of the semiconductor device;
depositing a first high-k dielectric layer (125, Figs. 24A-24C, ¶¶ [0079-0080]) over a backside (125, 129, 130, Fig. 24C) of the semiconductor device,
forming a first backside metal feature (130, Figs. 26A-C, ¶¶ [0082-0083]) in the first high-k dielectric layer;
Huang is silent regarding a thermal conductivity of the first high-k dielectric layer is greater than about 1.4 W/mK;
Wagner, in the same field of endeavor, discloses (Fig 1, ¶ [0038]) the backside metallization layer stack 120 may comprise a material with a thermal conductivity of at least 1 W/mK, at least 2 W/mK or at least 3 W/mK.for heat dissipation.
Therefore, it would be predictable for artisans in the art to adopt the back side dielectric thermal conductivity of Wagner to the back side dielectric thermal conductivity of Huang for heat dissipation. Absent unpredictable result, one of ordinary skill in the art would have selected the dielectric thermal conductivity to be greater than 1.4 W/mK through routine optimization.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to select a thermal conductivity greater than 1.4 W/mK from the disclosed range of Wagner to apply for the backside dielectric of Huang for optimal heat dissipation. Doing so would allow for a variety of material being selected for optimal applications.
Regarding claim 11, Huang in view of Wagner discloses the method of claim 10. Though not disclosing the thermal conductivity of the first high-k dielectric layer is in a range from about 50 W/mK to about 1200 W/mK. Wagner discloses the dielectric thermal conductivity is typically at least 1W/mK, at least 2W/mK or at least 3W/mK for heat dissipation (Wagner: ¶ [0038]). Artisans in the field would have selected a thermal conductivity of the first high-k dielectric layer in a range of 50W/mK-1200W/mK to yield predictable results for optimal applications. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select a range of thermal conductivity for the first high-k dielectric layer to be 50W/mK-1200W/mK out of the range of at least 1W/mK through routine optimization. Doing so would help improve thermal management and performance.
Regarding claim 12, Huang in view of Wagner discloses the method of claim 10. Though being silent regarding the thermal conductivity of the first high-k dielectric layer is greater than a thermal conductivity of the frontside dielectric layer, Huang discloses the front side dielectric and the backside dielectric are of the same material (¶ [0084]). It would be predictable for one of ordinary skill in the art to select two different dielectric layers for the frontside and the backside and the backside dielectric thermal conductivity is greater than that of the front size because the backside interconnects often comprise of power interconnection network. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select the backside dielectric thermal conductivity to be greater than that of the front side for optimal operations. Doing so would allow material’s ability to sustain heat endurance over long periods of exposure to high temperature induced by electrical components in the backside.
Regarding claim 13, Huang in view of Wagner discloses the method of claim 10. Huang further discloses depositing a second high-k dielectric layer (132, Fig. 28F) over the first high-k dielectric layer (125), and forming a second backside metal feature (134) in the second high-k dielectric layer and
over the first backside metal feature (130).
Huang is silent regarding a thermal conductivity of the second high-k dielectric layer is greater than about 1.4 W/mK;
Wagner, in the same field of endeavor, discloses (Fig 1, ¶ [0038]) the backside metallization layer stack 120 may comprise a material with a thermal conductivity of at least 1 W/mK, at least 2 W/mK or at least 3 W/mK for heat dissipation.
Therefore, it would be predictable for artisans in the art to adopt the back side dielectric thermal conductivity of Wagner to the second back side dielectric thermal conductivity of Huang for heat dissipation. Absent unpredictable result, one of ordinary skill in the art would have selected the dielectric thermal conductivity to be greater than 1.4 W/mK through routine optimization.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to select a thermal conductivity greater than 1.4 W/mK from the disclosed range of Wagner to apply for the second backside dielectric of Huang for optimal heat dissipation.
Regarding claim 14, Huang in view of Wagner discloses the method of claim 13. Though being silent regarding the thermal conductivity of the second high-k dielectric layer is greater than a thermal conductivity of the frontside dielectric layer, Huang discloses the front side dielectric and the second backside dielectric are of the same material (¶ [0084]). It would be predictable for one of ordinary skill in the art to select two different dielectric layers for the frontside and the backside and the backside dielectric thermal conductivity is greater than that of the front size because the backside interconnects often comprise of power interconnection network. As such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select the second backside dielectric thermal conductivity to be greater than that of the front side for optimal operations. Doing so would allow material to sustain heat endurance over long periods of exposure to high temperature caused by dense electrical components in the backside.
Regarding claim 17, Huang discloses the integrated circuit structure of claim 15 but is silent regarding wherein a thermal conductivity of the backside dielectric layer is in a range from about 50 W/mK to about 1200 W/mK.
Wagner, in the same field of endeavor, discloses (Fig 1, ¶ [0038]) the backside metallization layer stack 120 may comprise a material with a thermal conductivity of at least 1 W/mK, at least 2 W/mK or at least 3 W/mK.for heat dissipation.
Therefore, it would be predictable for artisans in the art to adopt the back side dielectric thermal conductivity of Wagner to the back side dielectric thermal conductivity of Huang for heat dissipation. Absent unpredictable result, one of ordinary skill in the art would have selected the dielectric thermal conductivity in a range from about 50 W/mK to about 1200 W/mK out of a range of greater than 1W/mK through routine optimization.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to select a thermal in a range from about 50 W/mK to about 1200 W/mK from the disclosed range of Wagner to apply for the backside dielectric of Huang for optimal heat dissipation.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20220359375 A1) in view of Sharma (US 20240215256 A1)
Regarding claim 19, Huang discloses the integrated circuit structure of claim 15, wherein the backside dielectric layer and the backside metal line form a backside interconnect structure but is silent regarding the integrated circuit structure further comprising: an interposer structure bonded with the backside interconnect structure.
Sharma, in the same field of endeavor, discloses (Fig. 10, 0114]) a metal interposer is bonded to backside of a device to accommodate the process flow of the device backside. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply the disclosure of Sharma to the IC of Huang to support the process flow of the backside of the device. Doing so would allow for a dense, high speed interposer to route signals between multiple chips and dies, increasing high bandwidth and reducing latency.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Liao (US 20210336063 A1) (Fig. 21) and Chen (US 20230154870 A1) disclose an IC device with frontside and backside interconnections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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