DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/24/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 through 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first semiconductor element" in line 11. There is insufficient antecedent basis for this limitation in the claim. The precedent citation recites “at least one first semiconductor element” in line 4.
Claim 1 recites the limitation "the first semiconductor element" in line 14. There is insufficient antecedent basis for this limitation in the claim. The precedent citation recites “at least one first semiconductor element” in line 4.
Claim 2 recites the limitation "the first semiconductor element" in line 10. There is insufficient antecedent basis for this limitation in the claim. The precedent citation recites “at least one first semiconductor element” in claim 1 line 4.
Claim 5 recites the limitation "the first semiconductor element" in line 3. There is insufficient antecedent basis for this limitation in the claim. The precedent citation recites “at least one first semiconductor element” in claim 1 line 4.
Claims 2 through 15 depend from and incorporate claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, 5, 7, 8, 9, and 11 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yoichi (JP 2017-054877, English translation submitted in IDS received 6/4/2024)
Regarding claim 1.
Yoichi teaches:
A semiconductor module (fig 11a:100e; [para 0079]) comprising:
a first conductive member (fig 11a:3; [para 0035]) including a first obverse surface facing in a thickness direction;
at least one first semiconductor element (fig 11a:1; [para 0035]) including a first electrode (fig 11a:1f; [para 0036]) and a first gate electrode (fig 11a:1s; [para 0036]) that face the first obverse surface and a second electrode (fig 11a:1t; [para 0036]) located on a side opposite to a side facing the first obverse surface in the thickness direction, the first electrode (fig 11a:1f; [para 0036]) being electrically connected to the first conductive member (fig 11a:3; [para 0035]);
and a heat transfer layer (fig 11a:2; [para 0080]) located between the first obverse surface and the first semiconductor element (fig 11a:1; [para 0035]), conductively bonded to the first obverse surface, and electrically connected to the first electrode (fig 11a:1f; [para 0036]), wherein the heat transfer layer (fig 11a:2; [para 0080]) includes a first surface facing the first obverse surface and a second surface facing the first semiconductor element (fig 11a:1; [para 0035]), the second surface is spaced apart from the first gate electrode (fig 11a:1s; [para 0036]) as viewed in the thickness direction, and the second surface is surrounded by a periphery of the first surface as viewed in the thickness direction.
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Regarding claim 2.
Yoichi teaches the semiconductor module according to claim 1, further
Yoichi teaches:
wherein the heat transfer layer (fig 11a:2; [para 0080]) includes a first layer including the first surface and conductively bonded to the first obverse surface and a second layer including the second surface and electrically connected to the first electrode (fig 11a:1f; [para 0036]), the second layer is located between the first layer and the first electrode (fig 11a:1f; [para 0036]), the first layer includes a third surface facing away from the first surface in the thickness direction, and the first semiconductor element (fig 11a:1; [para 0035]) is surrounded by a periphery of the third surface as viewed in the thickness direction.
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Regarding claim 3.
Yoichi teaches the semiconductor module according to claim 2, further
Yoichi teaches:
a dimension in the thickness direction of the first layer is greater than a dimension in the thickness direction of the second layer (fig 11a:T2; [para 0081,0082]).
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Regarding claim 4.
Yoichi teaches the semiconductor module according to claim 3, further
Yoichi teaches:
the dimension in the thickness direction of the first layer is 3 to 30 times the dimension in the thickness direction of the second layer (fig 11a:T2; [para 0081,0082]).
Regarding claim 5.
Yoichi teaches the semiconductor module according to claim 3, further
Yoichi teaches:
the second layer (fig 11a:T2; [para 0081,0082])
is surrounded by a periphery of the first semiconductor element (fig 11a,b:1; [para 0035]) as viewed in the thickness direction (fig 11b).
Regarding claim 7.
Yoichi teaches the semiconductor module according to claim 2, further
Yoichi teaches:
the second layer is spaced apart from the first gate electrode (fig 11a:1s; [para 0036]) as viewed in the thickness direction (fig 11a, annotated).
Regarding claim 8.
Yoichi teaches the semiconductor module according to claim 7, further
Yoichi teaches:
the first layer includes a fourth surface facing in a direction orthogonal to the thickness direction, the first layer is provided with a first recess (fig 11a:SP1; [para 0066]) that is recessed from the third surface and the fourth surface, and the first gate electrode (fig 11a:1s; [para 0036]) overlaps with the first recess (fig 11a:SP1; [para 0066]) as viewed in the thickness direction.
Regarding claim 9.
Yoichi teaches the semiconductor module according to claim 2, further
Yoichi teaches:
the heat transfer layer (fig 11a:2; [para 0080]) includes a first joining layer (fig 11a:S2; [para 0080]) conductively bonding the second surface and the first electrode (fig 11a:1f; [para 0036]), and a dimension in the thickness direction of the first joining layer (fig 11a:S2; [para 0080]) is smaller than the dimension in the thickness direction of the second layer (fig 11a).
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Regarding claim 11.
Yoichi teaches the semiconductor module according to claim 9, above.
Yoichi teaches:
the second layer (fig 11a:T2; [para 0081,0082]) is connected to the first layer at the third surface (fig 11a annotated above).
Claim(s) 16 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yoichi (JP 2017-054877, English translation)
Regarding claim 16.
Yoichi teaches:
A semiconductor device (fig 11a:100e; [para 0079]) comprising:
a semiconductor element (fig 11a:1; [para 0035]) including a first electrode (fig 11a:1f; [para 0036]) and a first gate electrode (fig 11a:1s; [para 0036]) that are located on one side in a thickness direction and a second electrode (fig 11a:1t; [para 0036]) located on another side in the thickness direction;
and a heat transfer layer (fig 11a:2; [para 0080]) facing the semiconductor element (fig 11a:1; [para 0035]) and electrically connected to the first electrode (fig 11a:1f; [para 0036]), wherein the heat transfer layer (fig 11a:2; [para 0080]) includes a first surface facing opposite to a side facing the semiconductor element (fig 11a:1; [para 0035]) in the thickness direction and a second surface facing the semiconductor element (fig 11a:1; [para 0035]), the second surface is spaced apart from the first gate electrode (fig 11a:1s; [para 0036]) as viewed in the thickness direction, and the second surface is surrounded by a periphery of the first surface as viewed in the thickness direction.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoichi (JP 2017-054877, English translation) as applied to claim 5 and further in view of Yoichi (JP 2017-054877, English translation)
Regarding claim 6.
Yoichi teaches the semiconductor module according to claim 5, further
Yoichi teaches:
an area of the second surface is smaller than an area of the [semiconductor element] (fig 11a,b:1; [para 0035]).
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Yoichi does not show the size of the first electrode in the embodiment.
Yoichi teaches a second embodiment:
The first electrode (fig 6ab:1f; [para 0036]) has substantially the same area as the semiconductor element (fig 6a,b:1; [para 0035])
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention an area of the second surface is smaller than an area of the first electrode in order to increase the bonding area of the first electrode (paragraph 61).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoichi (JP 2017-054877, English translation) as applied to claim 9 and further in view of Matsuo (US 2010/0148367).
Regarding claim 10.
Yoichi teaches the semiconductor module according to claim 9, above.
Yoichi teaches:
an interface between the second surface and the first joining layer (fig 11a:S2; [para 0080]) and an interface between the first joining layer (fig 11a:S2; [para 0080]) and the first electrode (fig 11a:1f; [para 0036]).
Yoichi does not teach solid phase diffusion bonding layers.
Matsuo teaches:
a solid-phase diffusion bonding layer (fig 4:silver,11,15; [para 0043]) exists at an interface between the second surface (fig 4:14; [para 0043]) and the first joining layer (fig 4:9; [para 0047]) and an interface between the first joining layer (fig 4:9; [para 0047]) and the first electrode (fig 4:10; [para 0047]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide solid phase diffusion bonding material (silver) in order to improve the wetting and adhesion of the bonding material.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoichi (JP 2017-054877, English translation) as applied to 16 and further in view of Soda (US 2017/0338189).
Regarding claim 17.
Yoichi teaches the semiconductor device according to claim 16, above
Yoichi teaches:
wherein the first surface (above annotated fig 11a) and the second electrode (fig 11a:1t; [para 0036]) are exposed
Yoichi does not teach sealing resin.
Soda teaches:
a sealing resin (fig 17:54; [para 0106]), wherein the first surface and the second electrode (fig 17:53; [para 0109])are exposed from the sealing resin (fig 17:54; [para 0106]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to embed the device in sealing resin in order to insulate and provide environmental stress resistance (paragraph 111).
Regarding claim 18.
Yoichi teaches:
a gate terminal (fig 11a:9; [para 0062]);
and a first redistribution wiring (fig 11a:10; [para 0043]) electrically connecting the gate terminal (fig 11a:9; [para 0042]) and the first gate electrode (fig 11a:1s; [para 0036]), wherein the gate terminal (fig 11a:9; [para 0042]) is located on the same side as the semiconductor element (fig 11a:1; [para 0035]) with respect to the heat transfer layer (fig 11a:2; [para 0080]) in the thickness direction,
Soda teaches
A gate terminal exposed from the sealing resin (fig 17:54; [para 0106])
And the redistribution wiring (fig 17:52; [para 0106])is at least partially covered with the sealing resin (fig 17:54; [para 0106])
Allowable Subject Matter
Claims 12, 13, 14, and 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 12, the prior art does not teach in combination with other elements of the claim a semiconductor module comprising: a semiconductor module comprising: comprising a heat transfer layer which includes a first surface and a second surface facing the first semiconductor element, the second surface is spaced apart from the first gate electrode as viewed in the thickness direction, and the second surface is surrounded by a periphery of the first surface as viewed in the thickness direction, a the heat transfer layer includes a second joining layer conductively bonding the first layer and the second layer, and a dimension in the thickness direction of the second joining layer is smaller than the dimension in the thickness direction of the second layer.
Regarding claim 14, the prior art does not teach in combination with other elements of the claim a semiconductor module comprising: comprising a heat transfer layer which includes a first surface and a second surface facing the first semiconductor element, the second surface is spaced apart from the first gate electrode as viewed in the thickness direction, and the second surface is surrounded by a periphery of the first surface as viewed in the thickness direction, a second conductive member including a second obverse surface facing a same side as the first obverse surface in the thickness direction; at least one second semiconductor element including a third electrode and a second gate electrode that are located on a side opposite to a side facing the second obverse surface in the thickness direction and a fourth electrode facing the second obverse surface, the fourth electrode being electrically connected to the second conductive member; and a third conductive member electrically connecting the second electrode and the third electrode, wherein a polarity of the first electrode and a polarity of the fourth electrode differ from each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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