Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9 and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on July 22, 2026.
Applicant's election with traverse of Species I in the reply filed on July 22, 2026 is acknowledged. The traversal is on the ground(s) that the burden for examining Species I-V together appears to be somewhat overstated. The examiner first notes that the applicant states the species are not obvious variants of each other, on page 2 paragraph 5 of the response filed on July 22, 2026. The examiner next notes the applicant’s arguments are conclusory in nature with the applicant generally describing some of the structural features of Species I-V but not specifically explaining why the distinct structural features of Species I-V as described in the Office action dated June 17, 2026 do not require different search strategies. The examiner further notes that the applicant being of the opinion that the variations between species are minor also does not explain why the distinct structural features of Species I-V do not require different search strategies. Therefore, the applicant’s arguments are not found persuasive because the applicant has not explained why the distinct structural features of Species I-V do not require different search strategies. However, the examiner withdraws the restriction requirement between Species I, II, IV, and V and Species II, IV, and V will be examined with species I. The claims readable on Species I, II, IV, and V are claims 1-8, 10-14, and 23. Therefore, claims 9 and 16-20 are directed toward non-elected species and are withdrawn from further consideration.
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 4, 2024 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: reference number 191. See paragraph 31. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The disclosure is objected to because of the following informalities: the specification contains the typographical error “UBM layer 118,” on page 9 paragraph 31. The UBM layer is understood to be referred to using reference number 192.
Appropriate correction is required.
Claim Objections
Claim 23 is objected to because of the following informalities: claim 23 contains the following typographical error “a first second chip pad connected to the first contact pad,” on page 8 lines 12-13. This limitation is understood to recite a first chip pad connected to the first contact pad. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 12, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2012/0018876) in view Ecton (US 2023/0197679) in view of Len et al. (US 2014/0091473) further in view of Chaing et al. (US 2016/0049359).
Regarding Claim 1:
Wu discloses a semiconductor package comprising:
a first semiconductor chip (substrate formed of semiconductor material with integrated circuits on the substrate, See figs. 1, 8, ref. nos. 10, 12, and paragraphs 11-12) comprising:
a semiconductor substrate (substrate formed of semiconductor material, See figs. 1, 8, ref. no. 10 and paragraph 11) having an active surface (second side, See fig. 1, ref. no. 10b and paragraphs 11-12. The examiner notes that the integrated circuits are formed on second side of the substrate, thus, the second side of the substrate is an active surface) and a first surface (first side, See fig. 1, ref. no. 10a and paragraph 12);
a device layer (interconnect structure on the second side, See figs. 1, 8, ref. no. 18 and paragraph 12) on the active surface;
first chip pads (under bump metallurgies connected to solder bumps 20, See figs. 1, 8, ref. no. 20 and paragraph 12) on the device layer; and
a first through-electrode (left through substrate via connected to under bump metallurgy 30B, See figs. 1, 8, ref. nos. 16, 30B, and paragraph 12) and a second through-electrode (right through substrate via connected to under bump metallurgy 30B, See figs. 1, 8, ref. nos. 16, 30B, and paragraph 12), wherein the first through-electrode and the second through-electrode penetrate the semiconductor substrate (the left through substate via and the right though substrate via, See figs. 1, 8, ref. nos. 10, 16, and paragraph 12), at least one of the first chip pads is connected to the first through-electrode (the second rightmost under bump metallurgy connected to a solder bump 20 is connected to the left through substrate via connected to under bump metallurgy 30B through the interconnect structure, See figs. 1, 8, ref. nos. 16, 18, 20, 30B) and at least one of the first chip pads is connected to the second through-electrode (the rightmost under bump metallurgy connected to a solder bump 20 is connected to the right through substrate via, See figs. 1, 8, ref. nos. 16, 18, 20, 30B);
a redistribution structure (interconnect structure, See figs. 1, 8, ref. no. 22 and paragraph 13)
under bump metallurgies on an upper surface (top surface of the interconnect structure, See figs. 1, 8, ref. nos. 22, 30B, and paragraph 14) of the redistribution structure; and
a second semiconductor chip (die, See fig. 8, ref. no. 38 and paragraph 16) on the redistribution structure and connected to the under bump metallurgies (the die is bonded to the under bump metallurgies 30B, See fig. 8, ref. nos. 30B, 36, 38 and paragraph 16),
wherein the under bump metallurgies comprise a first under bump metallurgy (second rightmost under bump metallurgy is connected to the left through substrate via through the interconnect structure, See figs. 1, 8, ref. nos. 16, 22 and 30B) connected to the first through-electrode through the redistribution layer and a second under bump metallurgy (rightmost under bump metallurgy vertically overlaps the right through substrate via, See figs. 1, 8, ref. nos. 16 and 30B) vertically overlapping the second through-electrode,
Wu does not disclose the first surface is an inactive surface, the redistribution structure comprises a redistribution layer on the inactive surface of the semiconductor substrate and a redistribution via connected to the redistribution layer, contact pads on an upper surface of the redistribution structure, the second semiconductor chip comprising second chip pads connected to the contact pads, wherein the contact pads comprise a first contact pad and a second contact pad, wherein the redistribution structure further comprises at least one post via penetrating the redistribution structure and connecting the second contact pad to the second through electrode and wherein the first contact pad comprises a contact via connected to the redistribution layer.
Ecton discloses a one-sided silicon die with through silicon via penetrating the one-sided silicon die (See fig. 1, ref. no. 114-1, 117, paragraphs 17 and 27-28. The examiner notes the a one-sided silicon die have one active surface and one passive surface.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu to make the integrated circuits and the semiconductor substrate as a one-sided silicon die as taught by Ecton in order or reduce the height of the semiconductor package.
The above stated combination of Wu and Ecton does not disclose the redistribution structure comprises a redistribution layer on the inactive surface of the semiconductor substrate and a redistribution via connected to the redistribution layer, contact pads on an upper surface of the redistribution structure, the second semiconductor chip comprising second chip pads connected to the contact pads, wherein the contact pads comprise a first contact pad and a second contact pad, wherein the redistribution structure further comprises at least one post via penetrating the redistribution structure and connecting the second contact pad to the second through electrode and wherein the first contact pad comprises a contact via connected to the redistribution layer.
Len discloses a redistribution structure comprises a redistribution layer (redistribution layer on a surface of a semiconductor die, See fig. 4, ref. nos. 130, 154, and paragraphs 36-38) on the inactive surface of the semiconductor substrate and a redistribution via (portion of the redistribution layer that penetrates the dielectric layer and connects the redistribution layer to the through substrate via, See fig. 4, ref. nos. 131, 154, 156, and paragraphs 36-38) connected to the redistribution layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu and Ecton to include the redistribution structure comprises a redistribution layer on the inactive surface of the semiconductor substrate and a redistribution via connected to the redistribution layer as taught by Len in order to attach semiconductor dies that have contacts are not aligned with the through substrate vias to the redistribution structure. (See Len paragraph 41.)
The above stated combination of Wu, Ecton, and Len does not disclose contact pads on an upper surface of the redistribution structure, the second semiconductor chip comprising second chip pads connected to the contact pads, wherein the contact pads comprise a first contact pad and a second contact pad, wherein the redistribution structure further comprises at least one post via penetrating the redistribution structure and connecting the second contact pad to the second through electrode and wherein the first contact pad comprises a contact via connected to the redistribution layer.
Len discloses contact pads (left metal post and right metal post on surface of redistribution structure, See fig. 4, ref. no. 159 and paragraphs 36-38) on an upper surface of the redistribution structure, the second semiconductor chip comprising second chip pads (left metal pad and right metal pad of the semiconductor die are shown in figure 4 as rectangular blocks above the under bump metallurgy, See fig. 4, ref. nos. 120A*, 147’’ and paragraph 36-38) connected to the contact pads, wherein the contact pads comprise a first contact pad (left metal post on surface of redistribution structure, See fig. 4, ref. no. 159 and paragraphs 36-38) and a second contact pad (right metal post on surface of redistribution structure, See fig. 4, ref. no. 159 and paragraphs 36-38), and wherein the first contact pad comprises a contact via (the tapered portion of the left metal post penetrates the dielectric layer and connects the metal posts to the redistribution layer, See Len fig. 4, ref. nos. 132, 154, 159, and paragraphs 38-39) connected to the redistribution layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, and Len to include contact pads on an upper surface of the redistribution structure, the second semiconductor chip comprising second chip pads connected to the contact pads, wherein the contact pads comprise a first contact pad and a second contact pad, and wherein the first contact pad comprises a contact via connected to the redistribution layer as taught by Len so that copper posts bonded together with a solder layer can be used to electrically connect the semiconductor die to the interconnect structure and thereby improve the electrical connection between the semiconductor die and the interconnect structure.
The above stated combination of Wu, Ecton, and Len does not disclose wherein the redistribution structure further comprises at least one post via penetrating the redistribution structure and connecting the second contact pad to the second through electrode.
Chiang discloses an integrally formed conductive pad and conductive post penetrating through a substrate to electrically connect to a circuit structure (See figs. 2D-2E, ref. nos. 20, 21, 25, 26, and paragraphs 49-53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, and Lu to include an integrally formed conductive pad and contact post penetrating the redistribution structure and connecting the second contact pad to the second through electrode as taught by Chiang in order to prevent delamination and cracking from occurring at interfaces between neighboring conductive structures. (See Chiang abstract and paragraph 33).
Regarding Claim 2:
The above stated combination of Wu, Ecton, Len, and Chiang discloses wherein the redistribution structure (redistribution structure, See Len fig. 4, ref. no. 132 and paragraph 36 The examiner notes that the redistribution layer of Len will be flipped upside down when placed on the first side surface of the substrate made of semiconductor material of Wu. See Wu, figs. 1, 8, ref. nos. 10a.) further comprises a first insulating layer (dielectric layer, See Len fig. 4, ref. no. 156 and paragraph 39) on an upper surface (surface of semiconductor die, See Len fig. 4, ref. no. 130 and paragraph 36) of the first semiconductor chip, and a second insulating layer (dielectric layer, See Len fig. 4, ref. no. 157 and paragraph 39) on the first insulating layer, wherein the redistribution layer (redistribution layer, See Len fig. 4, ref. no. 154 and paragraph 38) is on the first insulating layer, and wherein the redistribution via (portion of the redistribution layer that penetrates the bottom dielectric layer and connects the redistribution layer to the through substrate via, See Len fig. 4, ref. nos. 131, 154, 156, and paragraphs 36-38) penetrates the first insulating layer and connects the redistribution layer to the first through-electrode.
Regarding Claim 3:
The above stated combination of Wu, Ecton, Len, and Chiang discloses wherein the first contact pad and the second contact pad are on the second insulating layer, (the metal posts are on the top dielectric layer, See Len fig. 4, ref. nos. 157, 159, and paragraphs 38-39), wherein the contact via penetrates the second insulating layer and connects the first contact pad to the redistribution layer (the tapered portion of the left metal post penetrates the dielectric layer and connects the left metal post to the redistribution layer, See Len fig. 4, ref. nos. 132, 154, 159, and paragraphs 38-39) and wherein the at least one post via penetrates the first insulating layer and the second insulating layer (the conductive post penetrates completely through the substrate to electrically connect to a circuit structure, See Chiang figs. 2D-2E, ref. nos. 20, 21, 25, 26, and paragraphs 49-53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, and Lu to include an integrally formed conductive pad and contact post penetrating the first insulating layer and the second insulating layer as taught by Chiang in order to prevent delamination and cracking from occurring at interfaces between neighboring conductive structures. (See Chiang abstract and paragraph 33).
Regarding Claim 12:
The above stated combination of Wu, Ecton, Len, and Chiang discloses wherein the at least one post via has an integrated structure (conductive post and conductive pad are integrally formed, See Chiang figs. 2D-2E, ref. nos. 20, 21, 25, 26, and paragraphs 49-53).
Regarding Claim 23:
Wu discloses a semiconductor package comprising:
a first semiconductor chip (substrate formed of semiconductor material with integrated circuits on the substrate, See figs. 1, 8, ref. nos. 10, 12, and paragraphs 11-12) comprising:
a semiconductor substrate (substrate formed of semiconductor material, See figs. 1, 8, ref. no. 10 and paragraph 11) having an active surface (second side, See fig. 1, ref. no. 10b and paragraphs 11-12. The examiner notes that the integrated circuits are formed on second side of the substrate, thus, the second side of the substrate is an active surface) and a first surface (first side, See fig. 1, ref. no. 10a and paragraph 12);
a device layer (interconnect structure on the second side, See figs. 1, 8, ref. no. 18 and paragraph 12) on the active surface;
first chip pads (under bump metallurgies connect to solder bumps 20, See figs. 1, 8, ref. no. 20 and paragraph 12) on the device layer; and
through-electrodes (left through substrate via and right through substrate via connected to under bump metallurgies 30B and to the under bump metallurgies connected to solder bumps 20, See figs. 1, 8, ref. nos. 16, 20, 30B, and paragraph 12) penetrating the semiconductor substrate and connected to the first chip pads,
a redistribution structure (interconnect structure, See figs. 1, 8, ref. no. 22 and paragraph 13) on the first surface of the first semiconductor chip;
a first under bump metallurgy (second rightmost under bump metallurgy is connected to the left through substrate via through the interconnect structure, See figs. 1, 8, ref. nos. 16, 22 and 30B) and a second under bump metallurgy (rightmost under bump metallurgy is connected to the right through substrate via through the interconnect structure, See figs. 1, 8, ref. nos. 16, 22 and 30B) that are on an upper surface of the redistribution structure, wherein the second contact pad vertically overlaps one of the through-electrodes (the rightmost under bump metallurgy overlaps the right through substrate via, See figs. 1, 8, ref. nos. 16, 30B),
a second semiconductor chip (die, See fig. 8, ref. no. 38 and paragraph 16) on the redistribution structure and connected to the first under bump metallurgy and the second under bump metallurgy (the die is bonded to the under bump metallurgies 30B, See fig. 8, ref. nos. 30B, 36, 38 and paragraph 16).
Wu does not disclose the first surface is an inactive surface, a first contact pad and a second contact pad that are on an upper surface of the redistribution structure, wherein the second contact pad vertically overlaps one of the through-electrodes, the second semiconductor chip comprises a first chip pad connected to the first contact pad, and a second chip pad connected to the second contact pad, wherein the redistribution structure comprises: a first insulating layer on an upper surface of the first semiconductor chip; a redistribution layer on the first insulating layer; a redistribution via penetrating the first insulating layer and connecting the redistribution layer to the through-electrodes; and a second insulating layer on the first insulating layer and at least partially covering the redistribution layer, wherein the first contact pad is on the second insulating layer and comprises a contact via penetrating the second insulating layer and connected to the redistribution layer, and wherein the second contact pad is on the second insulating layer and comprises a post via penetrating the first insulating layer and the second insulating layer and connecting to the one through-electrode that is vertically overlapped by the second contact pad.
Ecton discloses a one-sided silicon die with through silicon via penetrating the one-sided silicon die (See fig. 1, ref. no. 114-1, 117, paragraphs 17 and 27-28. The examiner notes the a one-sided silicon die have one active surface and one passive surface.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu to make the integrated circuits and the semiconductor substrate as a one-sided silicon die as taught by Ecton in order or reduce the height of the semiconductor package.
The above stated combination of Wu and Ecton does not disclose a first contact pad and a second contact pad that are on an upper surface of the redistribution structure, wherein the second contact pad vertically overlaps one of the through-electrodes, the second semiconductor chip comprises a first chip pad connected to the first contact pad, and a second chip pad connected to the second contact pad, wherein the redistribution structure comprises: a first insulating layer on an upper surface of the first semiconductor chip; a redistribution layer on the first insulating layer; a redistribution via penetrating the first insulating layer and connecting the redistribution layer to the through-electrodes; and a second insulating layer on the first insulating layer and at least partially covering the redistribution layer, wherein the first contact pad is on the second insulating layer and comprises a contact via penetrating the second insulating layer and connected to the redistribution layer, and wherein the second contact pad is on the second insulating layer and comprises a post via penetrating the first insulating layer and the second insulating layer and connecting to the one through-electrode that is vertically overlapped by the second contact pad.
Len discloses a redistribution structure comprises: a first insulating layer (dielectric layer, See fig. 4, ref. no. 156 and paragraph 39) on an upper surface (surface of semiconductor die, See fig. 4, ref. no. 130 and paragraph 36) of the first semiconductor chip; a redistribution layer (redistribution layer, See fig. 4, ref. no. 154 and paragraph 38) on the first insulating layer; a redistribution via (portion of the redistribution layer that penetrates the dielectric layer and connects the redistribution layer to the through substrate via, See fig. 4, ref. nos. 131, 154, 156, and paragraphs 36-38) penetrating the first insulating layer and connecting the redistribution layer to the through-electrodes, and a second insulating layer (dielectric layer, See fig. 4, ref. no. 157 and paragraph 39) on the first insulating layer and at least partially covering the redistribution layer
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu and Ecton to include the redistribution structure comprises a first insulating layer on an upper surface of the first semiconductor chip; a redistribution layer on the first insulating layer; a redistribution via penetrating the first insulating layer and connecting the redistribution layer to the through-electrodes; and a second insulating layer on the first insulating layer and at least partially covering the redistribution layer, wherein the first contact pad is on the second insulating layer and comprises a contact via penetrating the second insulating layer and connected to the redistribution layer, as taught by Len in order to attach semiconductor dies that have contacts are not aligned with the through substrate vias to the redistribution structure. (See Len paragraph 41.)
The above stated combination of Wu, Ecton, and Len does not disclose a first contact pad and a second contact pad that are on an upper surface of the redistribution structure, wherein the second contact pad vertically overlaps one of the through-electrodes, the second semiconductor chip comprises a first chip pad connected to the first contact pad, and a second chip pad connected to the second contact pad and wherein the second contact pad is on the second insulating layer and comprises a post via penetrating the first insulating layer and the second insulating layer and connecting to the one through-electrode that is vertically overlapped by the second contact pad.
Len discloses a first contact pad (left metal post on surface of redistribution structure, See fig. 4, ref. no. 159 and paragraphs 36-38) and a second contact pad (right metal post on surface of redistribution structure, See fig. 4, ref. no. 159 and paragraphs 36-38) that are on an upper surface of the redistribution structure, wherein the second contact pad vertically overlaps one of the through-electrodes (the right metal post will be located in the right under bump metallurgy 30B of Wu, and thus, will vertically overlap the rightmost through substrate via 16 of Wu, See Len fig. 5, ref. no. 159 and Len figs. 1, 8, ref. nos. 16, 30B), the second semiconductor chip comprises a first chip pad (right metal pad of the semiconductor die are shown in figure 4 as rectangular blocks under the under bump metallurgy, See fig. 4, ref. nos. 120A*, 147’’ and paragraph 36-38) connected to the first contact pad, and a second chip pad (left metal pad of the semiconductor die are shown in figure 4 as rectangular block under the under bump metallurgy, See fig. 4, ref. nos. 120A*, 147’’ and paragraph 36-38) connected to the second contact pad, wherein the first contact pad is on the second insulating layer and comprises a contact via (the tapered portion of the left metal post penetrates the dielectric layer and connects the left metal post to the redistribution layer, See Len fig. 4, ref. nos. 132, 154, 257 159, and paragraphs 38-39) penetrating the second insulating layer and connected to the redistribution layer, and wherein the second contact pad is on the second insulating layer (right metal post is on the dielectric layer and connects the metal posts to the redistribution layer, See Len fig. 4, ref. nos. 132, 157, 159, and paragraphs 38-39).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, and Len to include a first contact pad and a second contact pad that are on an upper surface of the redistribution structure, wherein the second contact pad vertically overlaps one of the through-electrodes, the second semiconductor chip comprises a first chip pad connected to the first contact pad, and a second chip pad connected to the second contact pad, wherein the first contact pad is on the second insulating layer and comprises a contact via penetrating the second insulating layer and connected to the redistribution layer, and wherein the second contact pad is on the second insulating layer as taught by Len so that copper posts bonded together with a solder layer can be used to electrically connect the semiconductor die to the interconnect structure and thereby improve the electrical connection between the semiconductor die and the interconnect structure.
The above stated combination of Wu, Ecton, and Len, does not disclose wherein the second contact pad comprises a post via penetrating the first insulating layer and the second insulating layer and connecting to the one through-electrode that is vertically overlapped by the second contact pad.
Chiang discloses an integrally formed conductive pad and conductive post penetrating through a substrate to electrically connect to a circuit structure (See figs. 2D-2E, ref. nos. 20, 21, 25, 26, and paragraphs 49-53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Len, and Ecton to include the second contact pad comprises a post via penetrating the first insulating layer and the second insulating layer and connecting to the one through-electrode that is vertically overlapped by the second contact pad as taught by Chiang in order to prevent delamination and cracking from occurring at interfaces between neighboring conductive structures. (See Chiang abstract and paragraph 33).
Claims 4-8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2012/0018876), Ecton (US 2023/0197679), Len et al. (US 2014/0091473), and Chaing et al. (US 2016/0049359) in view of Mesch et al. (US 2023/0402390).
Regarding Claim 4:
The above stated combination of Wu, Ecton, Len, and Chiang discloses the above stated semiconductor package.
The above stated combination of Wu, Ecton, Len, and Chiang does not disclose wherein each of the at least one post via and the contact via has a vertical side surface.
Mesch discloses wherein each of the at least one post via (left via with vertical sidewalls, See fig. 8, ref.no. 842 and paragraphs 45-46 and 50-51) and the contact via (right via with vertical sidewalls, See fig. 8, ref.no. 842’ and paragraphs 45-46 and 50-51) has a vertical side surface.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, Len, and Chiang to include each of the at least one post via and the contact via has a vertical side surface as taught by Mesch in order to reduce the area occupied by the vias. (See Mesch paragraph 22.)
Regarding Claim 5:
The above stated combination of Wu, Ecton, Len, Chiang and Mesch discloses the above state semiconductor package.
The above stated combination of Wu, Ecton, Len, Chiang and Mesch does not disclose wherein a width of the at least one post via is smaller than a width of the contact via.
Mesch discloses wherein a width of the at least one post via is smaller than a width of the contact via (a width of left via with vertical sidewalls is smaller than a width of the right via with vertical sidewalls, See fig. 8, ref. nos. 842, 842’ and paragraphs 45-46 and 50-51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, Len, Chiang and Mesch to include a width of the at least one post via is smaller than a width of the contact via as taught by Mesch in order to reduce the area occupied by the post via. (See Mesch paragraph 22.)
Regarding Claim 6:
The combination of Wu, Ecton, Len, Chiang, and Mesch discloses wherein the redistribution via has a width that decreases vertically downward (portion of the redistribution layer that penetrates the dielectric layer and connects the redistribution layer to the through substrate via, See Len fig. 4, ref. nos. 131, 154, 156, and paragraphs 36-38. The examiner notes that this portion of the redistribution layer has a width that decreases vertically downward in the combination of Wu, Ecton, Len, Chiang and Mesch because redistribution structure of Len will be flipped upside down when placed on the first side surface of the substrate made of semiconductor material of Wu. See Wu, figs. 1, 8, ref. nos. 10a).
Regarding Claim 7:
The above stated combination of Wu, Ecton, Len, and Chiang discloses the above stated semiconductor package. The above stated combination of Wu, Ecton, Len, and Chiang further discloses wherein the contact via has an inclined side surface such that the contract via has width that decrease vertically downward (the tapered portion of the left metal post has an inclined side surface such that the tapered portion has a width that decreases vertically downward, See Len fig. 4, ref. no. 159. The examiner notes that the tapered portion of the left metal post has an inclined side surface such that the tapered portion has a width that decreases vertically downward in the combination of Wu, Len, Ecton, and Chiang because metal posts of Len will be flipped upside down when placed on the redistribution structure on the first side surface of the substrate made of semiconductor material of Wu. See Wu, figs. 1, 8, ref. nos. 10a).
The above stated combination of Wu, Ecton, Len, and Chiang does not disclose wherein the at least one post via has a vertical side surface.
Mesch discloses wherein the at least one post via (left via with vertical sidewalls, See fig. 8, ref.no. 842 and paragraphs 45-46 and 50-51) has a vertical side surface.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, Len, and Chiang to include the at least one post via has a vertical side surface as taught by Mesch in order to reduce the area occupied by the post via. (See Mesch paragraph 22.)
Regarding Claim 8:
The combination of Wu, Ecton, Len, Chiang, and Mesch discloses wherein the redistribution via has an inclined side surface such that the redistribution via has a width that decreases vertically downward (portion of the redistribution layer that penetrates the dielectric layer and connects the redistribution layer to the through substrate via, See Len fig. 4, ref. nos. 131, 154, 156, and paragraphs 36-38. The examiner notes that this portion of the redistribution layer has an inclined side surface such that the this portion has a width that decreases vertically downward in the combination of Wu, Ecton, Len, Chiang and Mesch because redistribution structure of Len will be flipped upside down when placed on the first side surface of the substrate made of semiconductor material of Wu. See Wu, figs. 1, 8, ref. nos. 10a).
Regarding Claim 10:
The above stated combination of Wu, Ecton, Len, and Chiang discloses the above stated semiconductor package.
The above stated combination of Wu, Ecton, Len, and Chiang does not disclose wherein the redistribution via has a vertical side surface.
Mesch discloses wherein the redistribution via (right via with vertical sidewalls, See fig. 8, ref.no. 842’ and paragraphs 45-46 and 50-51) has a vertical side surface.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, Len, and Chiang to include the redistribution via has a vertical side surface as taught by Mesch in order to reduce the area occupied by the redistribution via. (See Mesch paragraph 22.)
Regarding Claim 11:
The above stated combination of Wu, Ecton, Len, and Chiang discloses the above stated semiconductor package.
The above stated combination of Wu, Ecton, Len, and Chiang does not disclose wherein the at least one post via has a width that is greater than a width of the redistribution via.
Mesch discloses wherein the at least one post via (right via with vertical sidewalls, See fig. 8, ref.no. 842’ and paragraphs 45-46 and 50-51) has a width that is greater than a width of the redistribution via (left via with vertical sidewalls, See fig. 8, ref.no. 842 and paragraphs 45-46 and 50-51).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, Len, and Chiang to include the at least one post via has a width that is greater than a width of the redistribution via by Mesch in order to reduce the area occupied by the redistribution via. (See Mesch paragraph 22.)
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2012/0018876), Ecton (US 2023/0197679), Len et al. (US 2014/0091473), and Chaing et al. (US 2016/0049359) in view of Lin et al. (US 2023/0187365).
Regarding Claim 13:
The above stated combination of Wu, Ecton, Len, and Chiang discloses the above stated semiconductor package.
The above stated combination of Wu, Ecton, Len, and Chiang does not disclose wherein the first semiconductor chip further comprises a backside insulating layer having an upper surface that is substantially coplanar with an upper surface of the first through-electrode and an upper surface of the second through-electrode.
Lin discloses the first semiconductor chip (middle semiconductor IC chip, See fig. 12, ref. no. 100c and paragraph 215) further comprises a backside insulating layer (insulating bonding layer, See fig. 12, ref. no. 53 and paragraph 215) having an upper surface (top surface of the insulating bonding layer, See fig. 12, ref. no. 53) that is substantially coplanar with an upper surface of the first through-electrode and an upper surface of the second through-electrode (the insulating bonding layer has a top surface coplanar with a top surface of each of the through silicon vias, See fig. 12, ref. nos. 53, 157 and paragraph 215).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Wu, Ecton, Len, and Chiang to include the first semiconductor chip further comprises a backside insulating layer having an upper surface that is substantially coplanar with an upper surface of the first through-electrode and an upper surface of the second through-electrode as taught by Lin in order to protect the semiconductor chip from being damaged during fabrication of the interconnect structure.
Regarding Claim 14:
The above stated combination of Wu, Ecton, Len, Chiang, and Lin discloses wherein the redistribution structure further comprises a first connection pad (left metal pad on the through substrate via, See Len fig. 4, ref. no. 131 and paragraphs 36-38.) and a second connection pad (right metal pad on the through substrate via next to the through substrate via shown in figure 4, See figs. 3N, 4, and paragraphs 36-38. The examiner notes that figure 4 only shows a small portion of the package 100 and as shown in figure 3B the semiconductor die 130 will have multiple through substrate vias with metal pads below them.) on the first through-electrode and the second through-electrode, respectively, wherein the first connection pad (the left metal pad is connected to the redistribution layer through portion of the redistribution layer that penetrates the dielectric layer and is connected to the left metal post through the redistribution layer, See Len fig. 4, ref. nos. 132, 154, 156, 159) is connected to the redistribution layer through the redistribution via and is connected to the first contact pad through the redistribution layer, and wherein the second connection pad is connected to the second contact pad through the at least one post via (the conductive post penetrates completely through the substrate to electrically connect to a circuit structure, See Chiang figs. 2D-2E, ref. nos. 20, 21, 25, 26, and paragraphs 49-53).
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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