DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 1-12, is/are rejected under 35 U.S.C. 103 as being unpatentable over YANAGISAWA et al., US-20200381590-A1, in view of Lin et al., US-20220028924-A1.
Claim 1. YANAGISAWA et al., disclose a semiconductor device arrangement (such as the one in fig. 7), comprising:
-a substrate (item 14), comprising an upper surface (top side item 14);
-an adhesive structure (item 13), located on the upper surface and comprising a first region;
-a first semiconductor device (item 11), comprising: a lower surface (bottom side of 11), facing toward the adhesive structure;
-and a conductive bump (item 31), located under the lower surface and in the first region, and comprising a first portion and a second portion (as seen in the structure of fig. 7);
-wherein the lower surface does not contact the adhesive structure (as seen in the structure of fig. 7);
-wherein the first portion contacts the first region, and the second portion does not contact the first region (as seen in the structure of fig. 7).
As noted, YANAGISAWA et al., disclose the invention, except for the word “concave” with respect to the surface of the substrate.
However, in view of Fig. 1, [0023] of Lin et al., wherein is disclosed for example, the surface of the growth substrate 100 is patterned through a nanoimprinting process, such that the growth substrate 100 has a surface with concavity and convexity. It would have been prima facie obvious to have practiced well-known techniques from Lin to fabricate a semiconductor device arrangement including first concave region, and second concave region, because concave regions in semiconductor device surfaces are intentionally created to improve device performance, enable self-alignment, enhance integration density, or optimize electrical characteristics, and are formed through controlled lithography, etching, and deposition processes.
Claim 12. YANAGISAWA et al., disclose a method semiconductor device arrangement (such as the one in fig. 7), comprising:
-providing a substrate (item 14) comprising an upper surface (top side item 14);
-disposing an adhesive structure (item 13) on the upper surface;
-disposing a first semiconductor device (item 11), and a second semiconductor device (item 11) on the adhesive structure;
-providing an energy to the first semiconductor device such that a contact area between the first semiconductor device and the adhesive structure is reduced (this limitation would read through [0122] wherein is disclosed in Example Method 1, the amount of used SAP 30 may be reduced).
As noted, YANAGISAWA et al., appear to not disclose all the limitations such as “providing a transferring structure to contact the first semiconductor device and the second semiconductor device simultaneously; and removing the transferring structure to transfer the first semiconductor device to the transferring structure”.
However, in view of Fig. 1, [0054] of Lin et al., wherein is disclosed for example, in this embodiment, the first transfer substrate TS1 includes tape, and a viscosity of the adhesive layer AD2 is greater than a viscosity of the adhesive layer AD1 (or the tape). After the second transfer substrate TS2 is laminated on the light-emitting diode L1 on the first transfer substrate TS1 (e.g., the second transfer substrate TS2 is moved to be in contact with the light-emitting diode L1 and/or the first transfer substrate TS1 is moved such that the second transfer substrate TS2 is in contact with the light-emitting diode L1), the first transfer substrate TS1 is removed. Since the viscosity of the adhesive layer AD2 is greater than the viscosity of the adhesive layer AD1, after the first transfer substrate TS1 is removed, the light-emitting diode L1 remains on the second transfer substrate TS2.
It would have been prima facie obvious to have practiced well-known techniques from Lin to provide a transferring structure to contact the first semiconductor device and the second semiconductor device simultaneously; and removing the transferring structure to transfer the first semiconductor device to the transferring structure, because simultaneous contact and removal approach in semiconductor transfer is primarily driven by the need for faster, more uniform, and space‑efficient manufacturing while maintaining mechanical stability and integration compatibility for complex device architectures. This is especially important in high‑density display and microchip production, where speed, precision, and yield are critical.
fabricate a semiconductor device arrangement including first concave region, and second concave region, because concave regions in semiconductor device surfaces are intentionally created to improve device performance, enable self-alignment, enhance integration density, or optimize electrical characteristics, and are formed through controlled lithography, etching, and deposition processes.
Claim 2. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 1, further comprising a second semiconductor device which comprises a bonding pad, and wherein the adhesive structure further comprises a second concave region, and in a cross-sectional view, the bonding pad has roughly the same contour as that of the second concave region. This limitation would read through [0022] of Lin wherein is disclosed a light-emitting diode substrate 10 includes a growth substrate 100 and a light-emitting diode L. The light-emitting diode L includes a semiconductor stack layer SM and two electrodes E1 and E2.
Claim 3. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 2, wherein the bonding pad comprises a first outer surface, the conductive bump comprises a second outer surface, and the first outer surface comprises a concave portion or a texture rougher than that of the second outer surface.
This limitation would read through [0061] of Lin wherein is disclosed the circuit substrate 200 includes a plurality of pads P. The position of each of the light-emitting diodes L1, L2, and L3 corresponds to two pads P of the circuit substrate 200. In some embodiments, the pads P are electrically connected to active elements (not shown) or signal lines (not shown) in the circuit substrate 200.
Claim 4. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 2, wherein the adhesive structure comprises a first sub-adhesive structure and a second sub-adhesive structure separated from each other, the first semiconductor device is located on the first sub-adhesive structure, and the second semiconductor device is located on the second sub-adhesive structure.
This limitation would read through [0054] of Lin wherein is disclosed the first transfer substrate TS1 includes tape, and a viscosity of the adhesive layer AD2 is greater than a viscosity of the adhesive layer AD1 (or the tape). After the second transfer substrate TS2 is laminated on the light-emitting diode L1 on the first transfer substrate TS1 (e.g., the second transfer substrate TS2 is moved to be in contact with the light-emitting diode L1 and/or the first transfer substrate TS1 is moved such that the second transfer substrate TS2 is in contact with the light-emitting diode L1), the first transfer substrate TS1 is removed. Since the viscosity of the adhesive layer AD2 is greater than the viscosity of the adhesive layer AD1, after the first transfer substrate TS1 is removed, the light-emitting diode L1 remains on the second transfer substrate TS2.
Claim 5. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 1, wherein the first adhesive structure comprises a first maximum width, the first semiconductor device comprises a second maximum width, and the first maximum width is substantial the same as the second maximum width.
This limitation would read through [0054] of Lin wherein is disclosed the first transfer substrate TS1 includes tape, and a viscosity of the adhesive layer AD2 is greater than a viscosity of the adhesive layer AD1 (or the tape). After the second transfer substrate TS2 is laminated on the light-emitting diode L1 on the first transfer substrate TS1 (e.g., the second transfer substrate TS2 is moved to be in contact with the light-emitting diode L1 and/or the first transfer substrate TS1 is moved such that the second transfer substrate TS2 is in contact with the light-emitting diode L1), the first transfer substrate TS1 is removed. Since the viscosity of the adhesive layer AD2 is greater than the viscosity of the adhesive layer AD1, after the first transfer substrate TS1 is removed, the light-emitting diode L1 remains on the second transfer substrate TS2.
Claims 6-7. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 1, further comprising a plurality of particles discretely distributed within the conductive bump. This limitation would read through [0086-0087] of YANAGISAWA wherein is disclosed in order to form the bump 31 by using SAP 30, first, as shown in FIG. 8A, the SAP 30 may be applied to a surface on which the device-side electrode 12 is located. The SAP 30 includes a thermosetting resin 30a and metal powder 30b such as solder mixed into the thermosetting resin 30a. A shape of the metal powder 30b is not limited, and may be any shape such as a particulate shape or a plate shape. The same metal as the solder alloy may be used for the metal powder 30b of the SAP 30.
Claim 8. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 6, wherein the plurality of particles comprises gold, platinum, or alloys thereof. This limitation would read through [0028] of YANAGISAWA wherein is disclosed that each of the device-side electrode and a driver-side electrode formed on the driving substrate may include at least one of graphene, gold (Au), silver (Ag), copper (Cu), aluminum (Al), platinum (Pt), nickel (Ni), chromium (Cr), titanium (Ti), and indium tin oxide (ITO).
Claim 9. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 1, wherein the conductive bump is substantially a rectangle in a top view. This limitation would read through [0080] of YANAGISAWA wherein is disclosed a chip shape of each of the micro-LED 11 on which the device-side electrode 12 is formed may be a rectangular shape in a plan view.
Claim 10. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 1, further comprising a glue material on the first semiconductor device and separated from the conductive bump. This limitation would read through [0077] of YANAGISAWA wherein is disclosed the resin material that becomes the release layer 13 may include polyimide resin, acrylic resin for example PMMA, epoxy resin, PP resin, polycarbonate resin, and ABS resin, and the resin material is mixed with a thermal curing agent. Any of other thermosetting resins may be used as the resin material.
Claim 11. The combination of YANAGISAWA with Lin et al., disclose the semiconductor device arrangement according to claim 9, wherein a height of the glue material is smaller than a height of the conductive bump. This limitation would read through the structure of fig. 7 of YANAGISAWA.
Allowable Subject Matter
4. Claims 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 13, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of further comprising providing a mask with an opening, and providing the energy to the first semiconductor device by providing a laser energy to the first semiconductor device through the opening.
(B) Claim 14, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the opening corresponds to the first semiconductor device or a region larger than two of the first semiconductor devices.
(C) Claim 15, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the mask comprises a translucent substrate and a light-shielding layer located thereon.
(D) Claim 16, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the first semiconductor device comprises a bonding pad, and a contour of the bonding pad is changed after the step of providing an energy to the first semiconductor device.
(E) Claim 17, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the first semiconductor device comprises a lower surface, and the lower surface is separated from the adhesive structure after the step of providing an energy to the first semiconductor device.
(F) Claim 18, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of further comprising a target substrate, and transferring the first semiconductor device from the transferring structure to the target substrate by removing the transferring structure.
(G) Claim 19 is/are also allowable subject matter, as depend on claim 18.
(H) Claim 20, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of further comprising a step of retaining the second semiconductor device on the substrate after removing the transferring structure to transfer the first semiconductor device to the transferring structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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