Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 10 – 18 and 27 – 34 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/01/2025.
DETAILED ACTION
Claims 10 – 18 and 27 – 34 are withdrawn.
Claims 1 – 9 and 19 – 26 are pending.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/04/2024 was received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 5, 7 – 9, and 21 – 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the limitation “generate a bit having the same sequence as the at least one bit among bits of the read symbol as the second check bit” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same sequence”. Specifically, one of ordinary skill in the art would be unclear the relationship between “sequence”, indicating multiple elements, and “a bit”, singular.
Regarding claim 5, the limitation “perform a logic operation on a plurality of bits having the same sequence as the plurality of bits among bits of the read symbol to generate the second check bit.” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same sequence”. Specifically, one of ordinary skill in the art would be unclear if the “sequence”, is a logical relationship, positional relationship, or other relationship.
Regarding claim 7, the limitation “the read error check circuit is configured to generate the read error signal having a first voltage level when the first and second check bits have the same logic level, configured to generate the read error signal having a second voltage level when the first and second check bits have different logic levels and the first check bit has a first logic level, and configured to generate the read error signal having a third voltage level when the first and second check bits have different logic levels and the first check bit has a second logic level” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “bit” and “voltage level”. Specifically, one of ordinary skill in the art would understand a bit to be a binary value with only two potential voltage levels.
Regarding claim 8, the limitation “respectively” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the relationship between “the first and second check bits”.
Regarding claim 9, the limitation “respectively” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the relationship between “the first and second check bits”.
Regarding claim 21, the limitation “generate a bit having the same sequence as the at least one bit among bits of the first read symbol as the third check bit” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same sequence”. Specifically, one of ordinary skill in the art would be unclear the relationship between “sequence”, indicating multiple elements, and “a bit”, singular.
Regarding claim 22, the limitation “a logic operation on a plurality of bits having the same sequence as the plurality of bits among bits of the first read symbol to generate the third check bit.” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same sequence”. Specifically, one of ordinary skill in the art would be unclear if the “sequence”, is a logical relationship, positional relationship, or other relationship.
Regarding claim 23, the limitation “generate a bit having the same sequence as the at least one bit among bits of the second read symbol as the fourth check bit” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same sequence”. Specifically, one of ordinary skill in the art would be unclear the relationship between “sequence”, indicating multiple elements, and “a bit”, singular.
Regarding claim 24, the limitation “a logic operation on a plurality of bits having the same sequence as the plurality of bits among bits of the second read symbol to generate the fourth check bit.” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “same sequence”. Specifically, one of ordinary skill in the art would be unclear if the “sequence”, is a logical relationship, positional relationship, or other relationship.
Regarding claim 25, the limitation “the first read error check circuit is configured to generate the first read error signal having a first voltage level when one of the first and second check bits and the third check bit have the same logic level, configured to generate the first read error signal having a second voltage level when one of the first and second check bits and the third check bit have different logic levels and one of the first and second check bits has a first logic level, and configured to generate the first read error signal having a third voltage level when one of the first and second check bits and the third check bit have different logic levels and one of the first and second check bits has a second logic level” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “bit” and “voltage level”. Specifically, one of ordinary skill in the art would understand a bit to be a binary value with only two potential voltage levels.
Regarding claim 26, the limitation “the second read error check circuit is configured to generate the second read error signal having a first voltage level when the second and fourth check bits have the same logic level, configured to generate the second read error signal having a second voltage level when the second and fourth check bits have different logic levels and the second check bit has a first logic level, and configured to generate the second read error signal having a third voltage level when the second and fourth check bits have different logic levels and the second check bit has a second logic level” is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. One of ordinary skill in the art would be unclear the scope of “bit” and “voltage level”. Specifically, one of ordinary skill in the art would understand a bit to be a binary value with only two potential voltage levels.
Any claim not addressed above is rejected due to its dependency on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ware et al., U.S. Publication 2018/0351574 (herein Ware).
Regarding claim 1, Ware discloses: A semiconductor memory apparatus comprising: an encoding circuit configured to encode bank data output from a memory cell array to generate a read symbol and configured to generate a first check bit from the read symbol (figure 4, element 406; claim 15); a read path circuit configured to transmit the read symbol (figure 1, element 110); a transmitter circuit configured to generate a multi-level signal based on the read symbol received from the read path circuit, and configured to generate a second check bit from the read symbol (paragraph 0020, 0022, evaluation result that controls conditional reverse-inversion); and a read error check circuit configured to generate a read error signal based on the first check bit and the second check bit (paragraph 0020; claim 15).
Regarding claim 6, Ware discloses: a delay circuit configured to delay the first check bit, wherein a delay time of the delay circuit corresponds to a time at which the read symbol is transmitted from the encoding circuit to the transmitter circuit (paragraph 0016, 0020; figure 1, element 116, 120).
Allowable Subject Matter
Claim 19 and 20 are allowed.
Claims 2 – 5 and 7 – 9 are objected to as being dependent upon a rejected base claim.
Claims 2 – 5, 7 – 9, and 21 – 26 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Halbert; John B. et al. US 20170060680 A1
RYU; Yesin et al. US 20210193245 A1
Nagai; Takeshi US 20070226590 A1
TSUBOI; Yukitoshi et al. US 20150194984 A1
Kim; Jiho et al. US 20250181447 A1
Cha; Sanguhn et al. US 20200394102 A1
Kim; Hyunjoong et al. US 20210133028 A1
Lim; Jinsoo et al. US 20250036520 A1
Kim; Kiheung et al. US 11462292 B1
Cho; Sunghye et al. US 20210191810 A1
Cypher; Robert E. US 6973613 B2
a transmitter circuit configured to generate a multi-level signal based on the read symbol received from the read path circuit, and configured to generate a second check bit from the read symbol; and
a read error check circuit configured to generate a read error signal based on the first check bit and the second check bit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111