DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application filed on 06/04/2024.
Currently, claims 1-20 are examined as below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 06/04/2024. The IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
(Marked-Up Version) Semiconductor Device Having SiGe Anti-Diffusion Layers
(Clean Version) Semiconductor Device Having SiGe Anti-Diffusion Layers
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 is indefinite, because the limitation “a length a channel layer” in lines 9-10 renders the claim indefinite. It is unclear what “a length a channel layer” means. The limitation will be interpreted as “a length of a channel layer” for the purpose of examination.
Note the dependent claim 18 necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over US 2023/0180451 A1 to Lin et al. (“Lin”).
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Regarding independent claim 1, Lin in Figs. 4, 5E-2, 5F-2, 5G-2, 5O-1 and 5O-3 teaches a semiconductor device 100 (Figs 5O-1, 5O-3 & ¶ 48, semiconductor structure 100) comprising:
a substrate 102 (¶ 49, substrate 102);
an active region 104L (¶ 43, ¶ 59, lower fin element 104L are active regions, as element 104L is a part of the fin structures 104a-104d, which are active regions) extending in a first direction Y (Fig. 4, Y direction) on the substrate 102;
a plurality of channel layers 108, 109a, 109b (¶ 94, second semiconductor layers 108 form nanostructures 109a and 109b that serve as channel layers) stacked on the active region 104L and spaced apart from each other in a vertical direction Z (Figs. 4, 5O-1, 5O-3, Z direction) perpendicular to the first direction Y;
a gate structure 140 (¶ 127, gate stack 140) extending on the active region 104L in a second direction X (Figs. 4, 5O-1, 5O-3, X direction) perpendicular to the first direction Y and the vertical direction Z, and surrounding the plurality of channel layers 108, 109a, 109b (Figs. 5E-2, 5F-2, 5G-2, ¶ 233);
a source/drain region 124a, 124b (¶ 79, source/drain feature 124a ,124b) provided on at least one side of the gate structure 140 on the active region 104L (Fig. 5O-1) and electrically connected to the plurality of channel layers 108, 109a, 109b (Fig. 5O-1, ¶ 81, barrier layers 128 of the source/drain feature 124a, 124b has direct contact with the channel layers 108, 109a, 109b, which would form an electrical contact between these layers); and
a plurality of anti-diffusion layers 128 (¶ 84, barrier layers 128 on side surfaces of the layer 130 blocks the dopant from the layer 130 from diffusing into the layer 108) stacked and spaced apart from each other in the vertical direction Z and extending in the second direction X (Figs. 4, 5O-1),
wherein the plurality of anti-diffusion layers 128 comprise a SiGe (¶ 86, SiGe), and the plurality of anti-diffusion layers 128 are located only between the source/drain region 124a, 124b and the plurality of channel layers 108, 109a, 109b to discontinuously extend in the vertical direction Z (Figs. 4, 5O-1).
Lin does not explicitly disclose the SiGe of the anti-diffusion layers comprise a Si1-xGex layer (here, X ≠ 0).
However, Lin teaches a general condition in which the anti-diffusion layers comprise a SiGe (¶ 86), in which each of the silicon and the germanium would have an atomic fraction.
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, since Lin teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of the Si₁-xGeₓ layer (here, X ≠ 0) produce unexpected results that are different in kind and not different in degree, said general conditions taught by Lin renders claim 1 obvious.
Regarding claim 2, Lin does not explicitly disclose a thickness of each of the plurality of anti-diffusion layers in the first direction is about 0.1 nm to about 1 nm.
However, it would have been obvious to form the thickness within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 3, Lin in Fig. 5O-1 further teaches the plurality of anti-diffusion layers 128 are configured to prevent an N-type dopant (¶ 85, the bulk layer 130 of the source/drain feature 124a, 124b is doped with n-type dopant) diffusing from the source/drain region 124a, 124b from reaching the plurality of channel layers 108, 109a, 109b (¶ 84).
Regarding claim 4, Lin in Fig. 5O-1 further teaches the source/drain region 124a, 124b comprises a first layer 126 (¶ 81, undoped layer 126), a second layer 128 (Fig. 5O-1, ¶ 81, barrier layer 128 between the layers 126 and 130), and a third layer 130 (¶ 81, bulk layer 130) sequentially stacked from outside the active region 104L (Fig. 5O-1),
wherein the first layer 126, the second layer 128, and the third layer 130 comprise Si or SiC (¶ 82, ¶ 85, Si), and
wherein the second layer 128 is doped with an N-type dopant (¶ 85) at a first concentration (¶ 83) and the third layer 130 is doped with an N-type dopant (¶ 85) at a second concentration (¶ 83) different from the first concentration.
Regarding claim 5, Lin in Fig. 5O-1 further teaches the first layer 126 comprises an undoped Si layer 126 (¶ 82).
Regarding claim 6, Lin in Fig. 5O-1 further teaches the N-type dopant doped in the second layer 128 comprises arsenic (As) (¶ 85).
Regarding claim 7, Lin in Fig. 5O-1 further teaches the N-type dopant doped in the third layer 130 comprises phosphorus (P), arsenic (As), or a mixture thereof (¶ 85).
Regarding claim 8, Lin in Figs. 4 and 5O-1 further teaches the gate structure 140 comprises:
a gate electrode 146 (¶ 101, metal gate electrode layer 146) extending in the second direction X on the active region 104L (Figs. 4, 5O-1);
a gate insulating layer 144 (¶ 99, gate dielectric layer 144) surrounding the gate electrode 146 (Fig. 5O-1); and
a gate spacer 118 (¶ 68, gate spacer layer 118) covering a side of the gate insulating layer 144 (Fig. 5O-1),
wherein the gate electrode 146 comprises a main gate electrode 146 (¶ 101) extending in the second direction X on the plurality of channel layers 108, 109a, 109b and at least one sub-gate electrode 146 (¶ 101, metal gate electrode layer 146) located between each of the plurality of channel layers 108, 109a, 109b (Fig. 5O-1),
wherein the source/drain region 124a, 124b faces the plurality of channel layers 108, 109a, 109b with the plurality of anti-diffusion layers 128 therebetween in the first direction Y (Figs. 4, 5O-1), and
wherein the plurality of anti-diffusion layers 128 are offset from regions between the source/drain region 124a, 124b and the sub-gate electrode 146 (Fig. 5O-1).
Regarding claim 9, Lin in Fig. 5O-1 further teaches internal spacers 122 (¶ 63, inner spacer layers 122) located between the sub-gate electrode 146 and the source/drain region 124a ,124b on the active region 104L and spaced apart from each other in the vertical direction Z (Fig. 5O-1).
Regarding independent claim 19, Lin in Figs. 4, 5E-2, 5F-2, 5G-2, 5O-1 and 5O-3 teaches a semiconductor device 100 (Figs 5O-1, 5O-3 & ¶ 48, semiconductor structure 100) comprising:
an active region 104L (¶ 43, ¶ 59, lower fin element 104L are active regions, as element 104L is a part of the fin structures 104a-104d, which are active regions) extending in a first direction Y (Fig. 4, Y direction) on a substrate 102 (¶ 49, substrate 102);
a plurality of channel layers 108, 109a, 109b (¶ 94, second semiconductor layers 108 form nanostructures 109a and 109b that serve as channel layers) spaced apart from each other in a vertical direction Z (Figs. 4, 5O-1, 5O-3, Z direction) perpendicular to the first direction Y on the active region 104L and facing an upper surface of the active region 104L (Fig. 5O-1);
source/drain regions 124a, 124b (¶ 79, source/drain feature 124a ,124b) located on both sides of the plurality of channel layers 108, 109a, 109b on the active region 104L and electrically connected to the plurality of channel layers 124a, 124b (Fig. 5O-1, ¶ 81, barrier layers 128 of the source/drain feature 124a, 124b has direct contact with the channel layers 108, 109a, 109b, which would form an electrical contact between these layers); and
a plurality of anti-diffusion layers 128 (¶ 84, barrier layers 128 on side surfaces of the layer 130 blocks the dopant from the layer 130 from diffusing into the layer 108) spaced apart from each other in the vertical direction Z on the active region 104L and extending in a second direction X (Figs. 4, 5O-1, 5O-3, X direction) perpendicular to the first direction Y,
wherein the plurality of anti-diffusion layers comprise 128 comprise a SiGe (¶ 86, SiGe),
wherein the plurality of anti-diffusion layers 128 are provided between a source/drain region 124a, 124b (¶ 79, source/drain feature 124a ,124b), among the source/drain regions 124a, 124b, and the plurality of channel layers 108, 109a, 109b and discontinuously extend in the vertical direction Z (Fig. 5O-1),
wherein the plurality of anti-diffusion layers 128 are configured to prevent an N-type dopant (¶ 85, the bulk layer 130 of the source/drain feature 124a, 124b is doped with n-type dopant) diffusing from the source/drain region 124a, 124b from reaching the plurality of channel layers 108, 109a, 109b (¶ 84),
wherein the source/drain region 124a, 124b comprises a first layer 126 (¶ 81, undoped layer 126), a second layer 128 (Fig. 5O-1, ¶ 81, barrier layer 128 between the layers 126 and 130), and a third layer 130 (¶ 81, bulk layer 130) sequentially stacked from outside the active region 104L (Fig. 5O-1),
wherein the first layer 126, the second layer 128, and the third layer 130 comprise an Si layer (¶ 82, ¶ 85, Si),
wherein the second layer 128 doped with an N-type dopant (¶ 85) at a first concentration (¶ 83) and the third layer 130 is doped with an N-type dopant (¶ 85) at a second concentration different from the first concentration (¶ 83), and
wherein, when viewed in the second direction X, a portion of one of the plurality of anti-diffusion layers 128 facing the source/drain region 124a, 124b has a rounded circular arc shape (Fig. 5O-1).
Lin does not explicitly disclose the SiGe of the anti-diffusion layers comprise a Si1-xGex layer (here, X ≠ 0).
However, Lin teaches a general condition in which the anti-diffusion layers comprise a SiGe (¶ 86), in which each of the silicon and the germanium would have an atomic fraction.
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, since Lin teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of the Si₁-xGeₓ layer (here, X ≠ 0) produce unexpected results that are different in kind and not different in degree, said general conditions taught by Lin renders claim 19 obvious.
Regarding claim 20, Lin in Figs. 4, 5O-1 and 5O-3 further teaches a main gate electrode 146 (¶ 101, metal gate electrode layer 146) extending in the second direction X on the plurality of channel layers 108, 109a ,109b (Figs. 4, 5O-1);
a sub-gate electrode 146 (¶ 101, metal gate electrode layer 146) integrally connected to the main gate electrode 146 (Fig. 5O-1), and located between the substrate 102 and the plurality of channel layers 108, 109a, 109b (Fig. 5O-1);
a gate insulating layer 144 (¶ 99, gate dielectric layer 144) surrounding each of the main gate electrode 146 and the sub-gate electrode 146 (Fig. 5O-1);
a gate capping layer 148 (Figs. 5O-1, 5O-3, ¶ 110, metal capping layer 148) provided on the main gate electrode 146; and
internal spacers 122 (¶ 63, inner spacer layers 122) located between the sub-gate electrode 146 and the source/drain region 124a ,124b on the active region 104L (Fig. 5O-1), spaced apart from each other in the vertical direction Z (Fig. 5O-1), and extending in the second direction X (Figs. 4, 5O-1),
wherein the source/drain region 124a, 124b faces the plurality of channel layers 108, 109a, 109b with the plurality of anti-diffusion layers 128 therebetween in the first direction Y (Figs. 4, 5O-1), and
wherein the plurality of anti-diffusion layers 128 are offset from regions between the source/drain region 124a, 124b and the sub-gate electrode 146 (Fig. 5O-1).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of US 2022/0181500 A to Ha et al. (“Ha”).
Regarding claim 10, Lin does not explicitly disclose a source/drain capping layer on an upper surface of the source/drain region in the vertical direction, wherein the source/drain capping layer comprises an undoped Si layer or a Si layer with an N-type dopant.
Ha recognizes a need for improving performance and reliability of semiconductor device (¶ 5). Ha satisfies the need by providing a source/drain capping layer 154 (Fig. 2, ¶ 96, capping semiconductor pattern 154) on an upper surface of a source/drain region 151-153 (Fig. 2, a collective of semiconductor patterns 151, 152, 153 of first source/drain pattern 150) in a vertical direction (Fig. 2), wherein the source/drain capping layer 154 comprises an undoped Si layer 154 (¶ 100).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the source/drain capping layer taught by Ha with the source/drain regions taught by Lin, so as to improve performance and reliability of semiconductor device (Ha: ¶ 5).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 11-16 are allowed.
Regarding independent claim 11, Lin in Figs. 4, 5E-2, 5F-2, 5G-2, 5O-1 and 5O-3 teaches a semiconductor device 100 (Figs 5O-1, 5O-3 & ¶ 48, semiconductor structure 100) comprising:
an active region 104L (¶ 43, ¶ 59, lower fin element 104L are active regions, as element 104L is a part of the fin structures 104a-104d, which are active regions) extending in a first direction X (Figs. 4, 5O-1, X direction) on a substrate 102 (¶ 49, substrate 102);
a plurality of source/drain regions 124a, 124b (¶ 79, source/drain feature 124a ,124b) provided on the active region 104L (Fig. 5O-1);
a plurality of channel layers 108, 109a, 109b (¶ 94, second semiconductor layers 108 form nanostructures 109a and 109b that serve as channel layers) provided on at least one side of each of the plurality of source/drain regions 124a, 124b in the first direction X (Figs. 4, 5O-1), electrically connected to the plurality of source/drain regions 124a, 124b (Fig. 5O-1), and spaced apart from each other in a vertical direction Z (Figs. 4, 5O-1, 5O-3, Z direction) perpendicular to the first direction X;
a plurality of anti-diffusion layers 128 (¶ 84, barrier layers 128 on side surfaces of the layer 130 blocks the dopant from the layer 130 from diffusing into the layer 108) located on both sides of each of the plurality of source/drain regions 124a, 124b on the active region 104L and spaced apart from each other in the vertical direction Z (Figs. 4, 5O-1);
a gate structure 140 (¶ 127, gate stack 140) extending in a second direction Y (Figs. 4, 5O-1) perpendicular to the first direction X and the vertical direction Z on the active region 104L, and surrounding the plurality of channel layers 108, 109a, 109b (Figs. 5E-2, 5F-2, 5G-2, ¶ 233); and
wherein a source/drain region 124a, 124b (¶ 79, source/drain feature 124a ,124b) of the plurality of source/drain regions 124a, 124b is bilaterally symmetrical based on a central axis of the source/drain region 124a, 124b (Fig. 5O-1),
wherein the plurality of anti-diffusion layers 128 comprise a SiGe (¶ 86, SiGe), and
wherein the plurality of anti-diffusion layers 128 are provided between the source/drain region 124a, 124b and the plurality of channel layers 108, 109a, 109b, and discontinuously extend in the vertical direction Z (Fig. 5O-1).
Lin does not explicitly disclose the SiGe of the anti-diffusion layers comprise a Si1-xGex layer (here, X ≠ 0).
However, Lin teaches a general condition in which the anti-diffusion layers comprise a SiGe (¶ 86), in which each of the silicon and the germanium would have an atomic fraction.
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, since Lin teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of the Si₁-xGeₓ layer (here, X ≠ 0) produce unexpected results that are different in kind and not different in degree, said general conditions taught by Lin renders claim 11 obvious.
Lin does not explicitly disclose a thickness of each of the plurality of anti-diffusion layers in the first direction is about 0.1 nm to about 1 nm.
However, it would have been obvious to form the thickness within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Lin does not explicitly disclose a source/drain capping layer on an upper surface of the plurality of source/drain regions in the vertical direction.
However, Ha recognizes a need for improving performance and reliability of semiconductor device (¶ 5). Ha satisfies the need by providing a source/drain capping layer 154 (Fig. 2, ¶ 96, capping semiconductor pattern 154) on an upper surface of a plurality of source/drain regions 151-153 (Fig. 2, a collective of semiconductor patterns 151, 152, 153 of first source/drain pattern 150) in a vertical direction (Fig. 2).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the source/drain capping layer taught by Ha with the source/drain regions taught by Lin, so as to improve performance and reliability of semiconductor device (Ha: ¶ 5).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 11, a plurality of channel layers provided on at least one side of and spaced apart from each of the plurality of source/drain regions in the first direction.
Therefore, independent claim 11 is allowed.
Claims 12-16 are allowed, because they depend from the allowed claim 11.
Claims 17-18 are rejected¸ but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 17-18 would be allowable, because they depend from the allowed claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2022/0190134 A1 to Jeong et al. relates to a semiconductor device including an active pattern including a lower pattern and a plurality of sheet patterns, a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns, and a source/drain pattern filling a source/drain recess formed on one side of the gate structure, in which the source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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