Prosecution Insights
Last updated: April 19, 2026
Application No. 18/733,458

SEMICONDUCTOR INSPECTION TOOL AND METHODS OF OPERATION

Non-Final OA §102§103
Filed
Jun 04, 2024
Examiner
PYO, KEVIN K
Art Unit
2878
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
98%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
746 granted / 857 resolved
+19.0% vs TC avg
Moderate +11% lift
Without
With
+10.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
27 currently pending
Career history
884
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
43.2%
+3.2% vs TC avg
§102
32.9%
-7.1% vs TC avg
§112
18.1%
-21.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 857 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 8 and 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kikuchi et al (US 6,801,650). Regarding claim 8, Kikuchi et al shows in Figs.4-5 the following elements of applicant’s claim: receiving a semiconductor workpiece (semiconductor wafer) on a stage of a semiconductor inspection tool (12); performing an inspection operation to inspect the semiconductor workpiece using the semiconductor inspection tool (Figs.4-5); and monitoring, using a monitoring system (41, 41A) mounted to the semiconductor inspection tool (Fig.5) a distance between the semiconductor workpiece and a bottom lens of the semiconductor inspection tool in association with the inspection operation (abstract). Regarding claims 13-14, the limitations therein are shown in Figs.4-5 of Kikuchi et al (col.2, lines 19-41). Regarding claim 15, Kikuchi et al shows in Figs.4-5 the following elements of applicant’s claim: an inspection device (12) comprising a bottom lens (40); and a lens monitoring system (41, 41A) comprising: a support member (41A) coupled with the inspection device; and a monitoring device (41) coupled with the support member. Regarding claim 16, the limitations therein are shown in Fig.5 of Kikuchi et al (note: it is similar to the arrangement shown in Fig.1A of applicant’s drawings). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi et al (US 6,801,650) in view of Imai (US 5,483,056). Regarding claim 1, , Kikuchi et al shows in Figs.4-5 the following elements of applicant’s claim: inspecting a semiconductor workpiece (semiconductor wafer) using a semiconductor inspection tool (12), wherein a monitoring system (41, 41A), mounted to the semiconductor inspection tool (Fig.5), monitors a distance between the semiconductor inspection tool and the semiconductor workpiece (abstract). Although Kikuchi et al does not specifically mention the feature of performing a semiconductor processing operation, such feature is well known in the art as disclosed by Imai (Figs.1-3) and it would have been obvious to one of ordinary skill in the art to utilize the teachings of Imai in the device of Kikuchi et al in view of the desire to effectively achieve the manufacture of a semiconductor device. Regarding claims 2-5, the limitations therein are shown in Figs.4-5 of Kikuchi et al (col.2, lines 19-41). Regarding claims 6-7, the limitations therein are shown in the device of Kikuchi et al (Figs.4-5) of Imai (Figs.1-3). Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kikuchi et al (US 6,801,650). Regarding claim 12, the specific type of a sensor utilized would have been obvious to one of ordinary skill in the art in view of meeting different design requirements and achieving the particular desired performance. Allowable Subject Matter Claims 9-11 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 9-10 and 20, although the prior art (i.e. Kikuchi et al; US 6,801,650) discloses a semiconductor inspection tool (12, 40) and a monitoring system (41, 41A), it fails to disclose or make obvious the claimed method or device comprising, in addition to the other recited features of the claim, the feature of rotating a monitoring device around an inspection device in the manner recited in claim 9 or 20. Regarding claims 17-19, the prior art fails to disclose or make obvious a semiconductor inspection tool comprising, in addition to the recited features of claims 15-16, the details and functions of an annular ring and/or a lens monitoring system in the manner recited in claims 17-19. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN K PYO whose telephone number is (571)272-2445. The examiner can normally be reached 9:00-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Georgia Y Epps can be reached at 571-272-2328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN K PYO/Primary Examiner, Art Unit 2878
Read full office action

Prosecution Timeline

Jun 04, 2024
Application Filed
Jan 04, 2026
Non-Final Rejection — §102, §103
Mar 09, 2026
Interview Requested
Mar 25, 2026
Applicant Interview (Telephonic)
Mar 25, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

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SCALABLE NANOIMPRINT MANUFACTURING OF FUNCTIONAL MULTI-LAYER METASURFACE DEVICES
2y 5m to grant Granted Mar 24, 2026
Patent 12588123
CYBER-PHYSICAL SYSTEM FOR REAL-TIME DAYLIGHT EVALUATION
2y 5m to grant Granted Mar 24, 2026
Patent 12571682
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM
2y 5m to grant Granted Mar 10, 2026
Patent 12566144
SEMICONDUCTOR INSPECTION APPARATUS
2y 5m to grant Granted Mar 03, 2026
Patent 12555757
SEMICONDUCTOR EQUIPMENT MONITORING APPARATUS, AND SEMICONDUCTOR EQUIPMENT INCLUDING THE SEMICONDUCTOR EQUIPMENT MONITORING APPARATUS
2y 5m to grant Granted Feb 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
98%
With Interview (+10.6%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 857 resolved cases by this examiner. Grant probability derived from career allow rate.

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