DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 4 is objected to because of the following informalities: Lines 1-2 of claim 4 recites “that that”, when only one “that” is necessary. Appropriate correction is required.
Claim 20 is objected to because of the following informalities: Line 2 of claim 20 recites a limitation of “…extends into and a past peripheral edge”, which should be “extends into and past a peripheral edge”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Line 7 of claim 1 recites the limitation of a “doped liner”. From the context of the claim, it is unclear as to whether this “doped liner” is referring to the “N+ poly-silicon (Si) liner” or another doped liner that has not been referenced in the claim. Therefore, a clarification is required for the term “doped liner”. Claims 2-5 are dependent upon claim 1 and are rejected as well.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16, 17, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al, US Patent Application Publication 2022/0005810.
Regarding claim 16, Kang teaches a semiconductor device, comprising:
a lateral semiconductor path 105 (figure 3I, [0054]);
a lateral capacitor 180 electrically coupled to the lateral semiconductor path ([0056-0057]); and
a doped liner 126 disposed between the lateral semiconductor path and the lateral capacitor (figure 3N).
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Regarding claim 17, Kang teaches the lateral capacitor is a double-sided capacitor having
(1) a first electrode 130 with at least an inner portion (the inner side portion) integral with top and bottom portions (as labeled in figure above) that extend laterally away from the lateral semiconductor path 105 (figure 3I),
(2) a second electrode 134 positioned between the top and bottom portions of the first electrode, and
(3) a high-K layer 132 disposed between the top and first electrodes; and
the doped liner 126 directly contacts and electrically couples to the inner portion of the first electrode (figure 3N).
Regarding claim 19, Kang teaches the doped liner includes a planar surface that contacts the lateral semiconductor path (figure 3I and 3N).
Claim(s) 16, 17, 19, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al, US Patent Application Publication 2022/0102358
Regarding claim 16, Park teaches a semiconductor device, comprising:
a lateral semiconductor path SP_1;
a lateral capacitor EL1/DL/EL2 electrically coupled to the lateral semiconductor path ([0056-0057]); and
a doped liner SP_2 [0038] disposed between the lateral semiconductor path and the lateral capacitor (figure 12).
Regarding claim 17, Park teaches the lateral capacitor is a double-sided capacitor having
(1) a first electrode EL1 with at least an inner portion integral with top and bottom portions that extend laterally away from the lateral semiconductor path SP_1,
(2) a second electrode EL2 positioned between the top and bottom portions of the first electrode, and
(3) a high-K layer DL disposed between the top and first electrodes; and
the doped liner SP_2 directly contacts and electrically couples to the inner portion of the first electrode (figure 11).
Regarding claim 19, Kang teaches the doped liner includes a planar surface that contacts the lateral semiconductor path (figure 3I and 3N).
Regarding claim 20, Kang teaches the doped liner includes a pointed portion that extends into and a past peripheral edge of the lateral semiconductor path (Figure 12).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al, US Patent Application Publication 2022/0005810.
Regarding claim 1, Kang teaches a memory device, comprising:
a double-sided, lateral capacitor having a first electrode 130 and a second electrode 134 with a high- dielectric (high-K) layer 132 disposed there between, wherein the first electrode at least partially surrounds the second electrode;
an access device 105 including a lateral semiconductor path coupled to the capacitor (figure 3I); and
an N+ poly-silicon (Si) liner 126 disposed between the capacitor and the access device, wherein the doped liner electrically connects the lateral semiconductor path to the first electrode (Note: [0054] teaches 126 as a doped layer made from polysilicon layer 105 with [0031] teaching that dopant material may be either an n-type or p-type, Therefore, it would be obvious to one of ordinary skill in the art to make a n-type semiconductor device depending upon device optimization figure 3N).
Regarding claim 2, Kang teaches the N+ poly-Si liner provides dopants for the lateral semiconductor path through diffusion (figure 3I).
Regarding claim 3, Kang teaches the N+ poly-Si liner has a planar surface that contacts the lateral semiconductor path (figure 3I).
Regarding claim 4, Kang teaches the N+ poly-Si liner has an inner portion that that protrudes into the lateral semiconductor path (Note: Kang meets this limitation since 126 is made from a portion of 105, which means that 126 protrudes into 105).
Allowable Subject Matter
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 18, the prior art fails to anticipate or render obvious the claimed invention including “...the doped liner includes integral anchoring structures that extend laterally past the inner portion and directly contacting the side portions of the first electrode....” in combination with the remaining limitations.
Regarding claim 18, Kang teaches the first electrode of the double-sided capacitor includes side portions that extend vertically between the top and bottom portions (and laterally away from the lateral semiconductor path as labeled in figure above).
Kang fails to teach “the doped liner includes integral anchoring structures that extend laterally past the inner portion and directly contacting the side portions of the first electrode” After performing a search, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 18 has been found to be allowable.
Claims 6-15 are allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art fails to anticipate or render obvious the claimed invention including “...selectively removing portions of the doped poly-Si material to expose the top and bottom portions of the first electrode, wherein the doped poly-Si material remains between the inner portion of the first electrode and the semiconductor path;...” in combination with the remaining limitations. Claims 7-15 are dependent upon claim 6 and are therefore allowable.
Regarding claim 6, Kang teaches a method of manufacturing a memory device, the method comprising:
forming a semiconductor path 105 of an access device in a layer of semiconductor material, wherein the layer of semiconductor material is disposed between dielectric layers 110 or 104 (figures 3A-H);
forming a capacitor housing slot 124 at a peripheral end of the access device, wherein the capacitor housing slot is defined by laterally extending slot dividers and an exposed peripheral end portion of the semiconductor path (figure 3H);
depositing a doped poly-Si material 126 in the capacitor housing slot, wherein the deposited doped poly-Si material directly contacts and at least partially covers the peripheral end portion of the semiconductor path (figure 3I);
forming a first electrode 130 of a capacitor in the capacitor housing slot, wherein the first electrode directly contacts the doped poly-Si material in the capacitor housing slot, and wherein the first electrode includes an inner portion closest to the semiconductor path and integral with top, bottom, and side portions that extend laterally away from the inner portion; and
depositing a high-K layer 132 on at least inner surfaces of the first electrode and a second electrode 134 on the high-K layer (Figure 3L and 3N).
Kang fails to teach selectively removing portions of the doped poly-Si material to expose the top and bottom portions of the first electrode, wherein the doped poly-Si material remains between the inner portion of the first electrode and the semiconductor path. After performing a search, no other prior art was found that would meet the limitations of this claims, either in anticipatory or in combination with other references. Therefore, claims 6-15 have been found to be allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QUOVAUNDA JEFFERSON whose telephone number is (571)272-5051. The examiner can normally be reached M-F 7AM-4PM.
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QVJ
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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