DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are currently pending in application 18/733,685.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheong et al. (US 2019/0304849 A1).
As per independent Claim 1, Cheong discloses a method (See at least Figs. 1-3, Para 0012), comprising:
receiving a set of chip quality characteristics for a chip during a testing phase of the chip, wherein the chip is a semiconductor and the testing phase occurs before a time when the chip is transported to a customer; aligning each chip quality characteristic in the set of chip quality characteristics with characteristic data of a chip quality model, wherein the chip quality model is a machine learning model (See at least Para 0027, “The prediction process 300 obtains current WAT, CP, CP re-bin and FT data from the production run in step 302, then feeds the data into the trained model object in step 304. Feature engineering is performed in step 306, and a prediction is made in step 308.”; See also Para 0028, Para 0030-0042);
generating an output of the chip quality model using the set of chip quality characteristics and respective characteristic data that is aligned; and communicating the output, wherein the output indicates a chip group parameter for the chip and indicates a system-level test (SLT) parameter for the chip, where the chip group parameter recommends a chip group (See at least Para 0028, “The trained model can output a wafer-map with recommendations (plus optionally a confidence score) for chips to be sent to specified test step (usually burn-in) or to be shipped without specified test. The output, in the form of recommendations, can be provided in various formats, such as CSV files, or ingested directly into customer database systems.”; See also Para 0060-0061 and Para 0063-0067).
As per Claim 2, Cheong discloses wherein the set of chip quality characteristics include one or more of a type of chip, a manufacturer parameter, an environment parameter, or a chip location parameter (See at least Para 0027, Para 0031-0033).
As per Claim 3, Cheong discloses wherein the chip is an integrated circuit (IC) or a system on a chip (SoC) (See at least Para 0003).
As per Claim 4, Cheong discloses wherein the output is communicated to a validator system, further comprising: validating the chip group parameter and the SLT parameter using training data; and updating the chip quality model with results of the validating (See at least Para 0035-0050).
As per Claim 5, Cheong discloses wherein the output is communicated to a system or a process that directs the chip, after a chip probing combined (CPC) test, to a final test (FT) without system-level testing when the SLT parameter indicates that system-level testing is to be bypassed (See at least Para 0028).
As per Claim 6, Cheong discloses wherein the method executes prior to a CPC test and the method executes during a transit time of the chip (See also Para 0060-0061 and Para 0063-0067).
As per Claim 7, Cheong discloses wherein the output further includes training chip quality characteristics and is utilized to update the chip quality model (See at least Para 0035-0050).
As per Claim 8, Cheong discloses wherein the aligning each chip quality characteristic further utilizes a set of training labels representing respective chip quality characteristics to improve results of the chip quality model (See at least Para 0031, Para 0035-0050).
As per Claim 9, Cheong discloses wherein the set of chip quality characteristics is preprocessed to remove outlier data elements and to normalize parameters representing chip quality characteristics within the set of chip quality characteristics (See at least Para 0040-0044).
As per Claim 10, Cheong discloses herein user inputs are utilized to modify the set of chip quality characteristics (See at least Para 0031-0033, Para 0035-0050).
As per independent Claim 11, Cheong discloses a system, comprising:
a receiver, operational to receive a set of chip quality characteristics for a chip during a testing phase of the chip, wherein the chip is a semiconductor; and a chip quality evaluator, implemented on one or more processors, and operational to align each chip quality characteristic in the set of chip quality characteristics with characteristic data of a chip quality model (See at least Para 0027-0028, Para 0030-0042),
generating an output from the chip quality model using the set of chip quality characteristics and respective characteristic data that is aligned, and communicate the output, wherein the output indicates a chip group parameter for the chip and the output indicates a system-level test (SLT) parameter for the chip, where the chip group parameter recommends a chip group (See at least Para 0028, Para 0060-0061 and Para 0063-0067).
As per Claim 12, Cheong discloses a machine learning system, operational to communicate with the chip quality evaluator and to execute the chip quality model using the set of chip quality characteristics to generate the output (See at least Para 0023-0026, ML Training).
As per Claim 13, Cheong discloses a training system, operational to utilize the output to update the chip quality model to improve an accuracy of the output (See at least Para 0035-0050).
As per Claim 14, Cheong discloses a validator system, operational to utilize the output to validate the output against the chip quality model (See at least Para 0035-0050).
As per Claim 15, Cheong discloses wherein the receiver is further operational to receive user input parameters, wherein the user input parameters include a weighting for each of the chip quality characteristics (See at least Para 0052-0053).
As per Claim 16, Cheong discloses a transceiver, operational to communicate the output to a chip sorter system or a chip testing processing system (See at least Para 0028).
As per independent Claim 17, Cheong discloses a computer program product having a series of operating instructions stored on a non-transitory computer-readable medium that directs a data processing apparatus when executed thereby to perform operations to generate an output for a chip (See at least Figs. 1-3, Para 0012, Para 0029), the operations comprising:
receiving a set of chip quality characteristics for the chip during a testing phase of the chip, wherein the chip is a semiconductor and the testing phase occurs before a time when the chip is transported to a customer; aligning each chip quality characteristic in the set of chip quality characteristics with characteristic data of a chip quality model, wherein the chip quality model is a machine learning model (See at least Para 0027-0028, Para 0030-0042);
generating the output of the chip quality model using the set of chip quality characteristics and respective aligned characteristic data; and communicating the output, wherein the output indicates a chip group parameter for the chip and indicates a system-level test (SLT) parameter for the chip, where the chip group parameter recommends a chip group (See at least Para 0028, Para 0060-0061 and Para 0063-0067).
As per Claim 18, Cheong discloses wherein the machine learning model is a deep learning neural network (See at least Para 0021).
As per Claim 19, Cheong discloses wherein the operations are performed on a chip testing system or a cloud environment (See at least Figs. 1-3, Para 0012, Para 0029).
As per Claim 20, Cheong discloses validating the output using training data; and updating the chip quality model using results from the validating (See at least Para 0035-0050).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure can be found in the PTO-892 Notice of References Cited. The Examiner suggests the applicant review all of these documents before submitting any amendments.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN P OUELLETTE whose telephone number is (571)272-6807. The examiner can normally be reached on M-F 8am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynda C Jasmin, can be reached at telephone number (571) 272-6782. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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July 27, 2026
/JONATHAN P OUELLETTE/Primary Examiner, Art Unit 3629
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