DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 06/04/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 06/04/2024 & 02/18/2025. The information disclosed therein was considered.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 3 & 13: the limitations cite “the third value is greater than the second value”, there is no support in the specification shown that the third value is greater than the second value.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 10, 13 & 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 3 & 13, the limitations cite “the third value is greater than the second value”, it is unclear how the third value can be greater than the second value when the third value in claim 1 is set to be between and unequal to the first and second values? Furthermore, there is no support in the specification shown that the third value is greater than the second value. For the purpose of persecution, it will be treated as “the third value is less than the second value” according to [0040] of the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s)1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al (US6331953) in view of Tran et al (US9).
Regarding in claim 1, Wang discloses a method of erasing a memory cell including a floating gate (FIG 5 & 11; col 14 line 57-65 discloses forward erase e.g., removing trapped charge, e.g., floating gate (charged trapped region)), comprising: applying successive first erase pulses to the memory cell (FIG 11; generating N+1 st pulses of coarse erase seq) to remove electrons from the floating gate until a coarse target read current for the memory cell is achieved(current vary from verified current by less than delta after verifying cell is not erased), wherein the first erase pulses include a first parameter following a first progression in which the first parameter changes in value after respective ones of the first erase pulses and wherein the first progression begins with a first value of the first parameter and ends with a second value of the first parameter(FIG 9; col 13 line 57 – col 14 line 16; discloses erase pluses T1-T3 with different VDs and VGs). ; and after the coarse target read current is achieved, applying successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved(generating M+1st pluses of fine erase seq if the verification is yes), wherein the second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses (FIG 10; col 14, lines 31-51; discloses applying sequence of ramped voltages applied to gate with a fine erase sequence until an initial charge has been removed from the charge trapped region, VD VG).
However, Wang does not disclose wherein the second progression begins with a third value of the first parameter that is between, and unequal to, the first and second values.
In the same field of endeavor, Tran discloses wherein the second progression begins with a third value of the first parameter that is between, and unequal to, the first and second values (FIG 49A-49B; [0218] discloses progression starting with a third value i e.g., middle that is between the first Parmenter e.g., start of values t1 ramp up and so on and end of second values e.g., t2).
Wang and Tran are analogous art because they are all directed to a non-volatile memory device with a floating gate and comprising a ramp up pulse erase operation, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Wang to include Tran because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Tran in the teachings of Wang for the benefits having a memory array that is erase and programed to hold a very specific and precise amount of charge in the floating gate that enables the non-volatile memory device to have an improved programming system. [0007-0008 Tran].
Regarding in claim 2, The combinations of Wang in view of Tran discloses wherein: the first parameter is a voltage applied to the memory cell; during the first progression, the voltage increases in value after respective ones of the first erase pulses, wherein the second value is greater than the first value(FIG 9 Vd T1-T3); during the second progression, the voltage increases in value after respective ones of the second erase pulses(FIG 10); and the third value is less than the second value (Tran FIG 49B, I is less than t2 value).
Regarding in claim 3, The combinations of Wang in view of Tran discloses wherein: the first parameter is a voltage applied to the memory cell(FIG 9); during the first progression, the voltage decreases in value after respective ones of the first erase pulses(FIG 9; Vg T1-T3), wherein the second value is less than the first value(as it goes into the negatives values T2 and less than T1); during the second progression, the voltage decreases in value after respective ones of the second erase pulses(FIG 10 on Vg); and the third value is greater than the second value(FIG 49A-49B; [02187] discloses progression starting with a third value i e.g., middle that is between the first Parmenter e.g., start of values t1 ramp up and so on and end of second values e.g., t2).
Regarding in claim 4, The combinations of Wang in view of Tran discloses wherein: the first parameter is a duration of respective ones of the first and second erase pulses(FIG 9; T1-T2); during the first progression, the duration increases in value after respective ones of the first erase pulses(delta changes from T1-T2), wherein the second value is greater than the first value(T2 is T1 + Delta);during the second progression, the duration increases in value after respective ones of the second erase pulses(Fig 10); and the third value is less than the second value(Tran FIG 49B, I is less than t2 value).
Regarding in claim 5, The combinations of Wang in view of Tran discloses wherein: during the first progression(delta changes from T1-T2), the first parameter changes in value by a first change value after respective ones of the first erase pulses(delta); during the second progression, the first parameter changes in value by a second change value after respective ones of the second erase pulses(FIG 10); and the second change value is equal to the first change value(same delta changes between T1-T2 on Vdd of FIG 9 & 10).
Regarding in claim 6, The combinations of Wang in view of Tran discloses wherein: during the first progression, the first parameter changes in value by a first change value after respective ones of the first erase pulses(FIG 9 delta change on Vg); during the second progression, the first parameter changes in value by a second change value after respective ones of the second erase pulses(FIG 10; delta change on Vg); and the second change value is less than the first change value(FIG 10 Vg in delta change is less than Vg In FIG 9 e.g., in negative direction changes).
Regarding in claim 7, The combinations of Wang in view of Tran discloses wherein the memory cell comprises: a source region and a drain region formed in a semiconductor substrate(FIG 5; 10 comprising substrate 12 and Source and drain), with a channel region of the semiconductor substrate extending between the source region and the drain region(18); a floating gate disposed over and insulated from a first portion of the channel region(20 comprising 68 disposed over 18 if first potion of the channel region); and a select gate disposed over and insulated from a second portion of the channel region, wherein the voltage applied to the memory cell is applied to the select gate (portion of channel gate is located e.g., by source area on 18 and voltage applied to gate).
Regarding in claim 8, The combinations of Wang in view of Tran discloses wherein the memory cell comprises: a source region and a drain region formed in a semiconductor substrate(FIG 5; 10 12 source and drain), with a channel region of the semiconductor substrate extending between the source region and the drain region(18); a floating gate disposed over and insulated from a first portion of the channel region(20, 68 over 18); a select gate disposed over and insulated from a second portion of the channel region(gate on source area); and an erase gate disposed over and insulated from the source region wherein the voltage applied to the memory cell is applied to the erase gate (Tran FIG 6; 30 EG).
Regarding in claim 9, The combinations of Wang in view of Tran discloses wherein the memory cell comprises: a source region and a drain region formed in a semiconductor substrate(FIG 5), with a channel region of the semiconductor substrate extending between the source region and the drain region(FIG 5; 18);a floating gate disposed over and insulated from a first portion of the channel region(20, 68 over 18); a select gate disposed over and insulated from a second portion of the channel region(Tran FIG 6-7; 22 SG); an erase gate disposed over and insulated from the source region(Tran FIG 6-7; 30 EG); and a control gate disposed over and insulated from the floating gate(Tran FIG 6-7; CG),wherein the voltage applied to the memory cell is applied to the erase gate. (voltage applied to 30 EG).
Regarding in claim 10, The combinations of Wang in view of Tran wherein the memory cell comprises: a source region and a drain region formed in a semiconductor substrate(FIG 5), with a channel region of the semiconductor substrate extending between the source region and the drain region(FIG 5; 18); a floating gate disposed over and insulated from a first portion of the channel region(20, 68 on 18); a select gate disposed over and insulated from a second portion of the channel region(Tran FIG 6-7; 22 SG); an erase gate disposed over and insulated from the source region(Tran 6-7; 30 EG) and a control gate disposed over and insulated from the floating gate(Tran FIG 6-7; CG), wherein the voltage applied to the memory cell is applied to the control gate(voltage applied to CG).
Regarding in claim 11, Wang discloses a semiconductor device, comprising: a memory cell including a floating gate(FIG 5 & 11; floating gate charged trapped region); and a control circuitry to(FIG 5; col 11 line 1-line 23; supported circuitry to operate FIG 5 e.g., control circuitry): apply successive first erase pulses (FIG 11; generating N+1 st pulse of coarse erase seq) to the memory cell to remove electrons from the floating gate until a coarse target read current for the memory cell is achieved(current vary from verified current by less than delta), wherein the first erase pulses include a first parameter following a first progression in which the first parameter changes in value after respective ones of the first erase pulses and wherein the first progression begins with a first value of the first parameter and ends with a second value of the first parameter(FIG 9; col 13 line 57 – col 14 line 16; discloses erase pluses T1-T3 with different VDs and VGs); and after the coarse target read current is achieved), apply successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved(generating M+1st pluses of fine erase seq if the verification is yes after verifying cell is not erased), wherein the second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses(FIG 10; col 14, lines 31-51; discloses applying sequence of ramped voltages applied to gate with a fine erase sequence until an initial charge has been removed from the charge trapped region VD VG).
However, Wang does not disclose wherein the second progression begins with a third value of the first parameter that is between, and unequal to, the first and second values.
In the same field of endeavor, Tran discloses wherein the second progression begins with a third value of the first parameter that is between, and unequal to, the first and second values (FIG 49A-49B; [0218] discloses progression starting with a third value i e.g., middle that is between the first Parmenter e.g., start of values t1 ramp up and so on and end of second values e.g., t2).
Wang and Tran are analogous art because they are all directed to a non-volatile memory device with a floating gate and comprising a ramp up pulse erase operation, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Wang to include Tran because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Tran in the teachings of Wang for the benefits having a memory array that is erase and programed to hold a very specific and precise amount of charge in the floating gate that enables the non-volatile memory device to have an improved programming system. [0007-0008 Tran].
Regarding in claim 12, The combinations of Wang in view of Tran discloses wherein: the first parameter is a voltage applied to the memory cell; during the first progression, the voltage increases in value after respective ones of the first erase pulses, wherein the second value is greater than the first value(FIG 9 Vd T1-T3); during the second progression, the voltage increases in value after respective ones of the second erase pulses(FIG 10); and the third value is less than the second value (Tran FIG 49B, I is less than t2 value).
Regarding in claim 13, The combinations of Wang in view of Tran discloses wherein: the first parameter is a voltage applied to the memory cell(FIG 9); during the first progression, the voltage decreases in value after respective ones of the first erase pulses(FIG 9; Vg T1-T3), wherein the second value is less than the first value(as it goes into the negatives values T2 and less than T1); during the second progression, the voltage decreases in value after respective ones of the second erase pulses(FIG 10 on Vg); and the third value is greater than the second value(FIG 49A-49B; [02187] discloses progression starting with a third value i e.g., middle that is between the first Parmenter e.g., start of values t1 ramp up and so on and end of second values e.g., t2).
Regarding in claim 14, The combinations of Wang in view of Tran discloses wherein: the first parameter is a duration of respective ones of the first and second erase pulses(FIG 9; T1-T2); during the first progression, the duration increases in value after respective ones of the first erase pulses(delta changes from T1-T2), wherein the second value is greater than the first value(T2 is T1 + Delta);during the second progression, the duration increases in value after respective ones of the second erase pulses(Fig 10); and the third value is less than the second value(Tran FIG 49B, I is less than t2 value).
Regarding in claim 15, The combinations of Wang in view of Tran discloses wherein: during the first progression(delta changes from T1-T2), the first parameter changes in value by a first change value after respective ones of the first erase pulses(delta); during the second progression, the first parameter changes in value by a second change value after respective ones of the second erase pulses(FIG 10); and the second change value is equal to the first change value(same delta changes between T1-T2 on Vdd of FIG 9 & 10).
Regarding in claim 16, The combinations of Wang in view of Tran discloses wherein: during the first progression, the first parameter changes in value by a first change value after respective ones of the first erase pulses(FIG 9 delta change on Vg); during the second progression, the first parameter changes in value by a second change value after respective ones of the second erase pulses(FIG 10; delta change on Vg); and the second change value is less than the first change value(FIG 10 Vg in delta change is less than Vg In FIG 9 e.g., in negative direction changes).
Regarding in claim 17, The combinations of Wang in view of Tran discloses wherein the memory cell comprises: a source region and a drain region formed in a semiconductor substrate(FIG 5; 10 comprising substrate 12 and Source and drain), with a channel region of the semiconductor substrate extending between the source region and the drain region(18); a floating gate disposed over and insulated from a first portion of the channel region(20 comprising 68 disposed over 18 if first potion of the channel region); and a select gate disposed over and insulated from a second portion of the channel region, wherein the voltage applied to the memory cell is applied to the select gate (portion of channel gate is located e.g., by source area on 18 and voltage applied to gate).
Regarding in claim 18, The combinations of Wang in view of Tran discloses wherein the memory cell comprises: a source region and a drain region formed in a semiconductor substrate(FIG 5; 10 12 source and drain), with a channel region of the semiconductor substrate extending between the source region and the drain region(18); a floating gate disposed over and insulated from a first portion of the channel region(20, 68 over 18); a select gate disposed over and insulated from a second portion of the channel region(gate on source area); and an erase gate disposed over and insulated from the source region wherein the voltage applied to the memory cell is applied to the erase gate (Tran FIG 6; 30 EG).
Regarding in claim 19, The combinations of Wang in view of Tran discloses wherein the memory cell comprises: a source region and a drain region formed in a semiconductor substrate(FIG 5), with a channel region of the semiconductor substrate extending between the source region and the drain region(FIG 5; 18);a floating gate disposed over and insulated from a first portion of the channel region(20, 68 over 18); a select gate disposed over and insulated from a second portion of the channel region(Tran FIG 6-7; 22 SG); an erase gate disposed over and insulated from the source region(Tran FIG 6-7; 30 EG); and a control gate disposed over and insulated from the floating gate(Tran FIG 6-7; CG),wherein the voltage applied to the memory cell is applied to the erase gate. (voltage applied to 30 EG).
Regarding in claim 20, The combinations of Wang in view of Tran wherein the memory cell comprises: a source region and a drain region formed in a semiconductor substrate(FIG 5), with a channel region of the semiconductor substrate extending between the source region and the drain region(FIG 5; 18); a floating gate disposed over and insulated from a first portion of the channel region(20, 68 on 18); a select gate disposed over and insulated from a second portion of the channel region(Tran FIG 6-7; 22 SG); an erase gate disposed over and insulated from the source region(Tran 6-7; 30 EG) and a control gate disposed over and insulated from the floating gate(Tran FIG 6-7; CG), wherein the voltage applied to the memory cell is applied to the control gate(voltage applied to CG).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Roohparvar et al (US20080310224 FIG 6; discloses S601, S603 S605 & S607; determining initial coarse programming pulses).
Bertuccio et al (US20240071484 FIG 3-4; [0057] discloses read window, and memory cells programmed to coarse target values are not read).
Tran et al (US202220215239 FIG 23; [0161] discloses determining a coarse target current value to each of selected cell based on a value that is intend to be stored).
Li et al (US20090073771 FIG 5; Claim 17; discloses read/write circuitry verifying memory cell to be programmed relative to coarse verify level).
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827