amezNotice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Election/Restrictions
Claims #17-19, 27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/09/2026.
Applicant Argues that, ‘In view of the above, Applicants submit that the search and examination of all the alleged Groups (e.g., Groups I through Group III) may be made without serious burden. Accordingly, Applicants respectfully request the Examiner to reconsider and withdraw the above requirement(s).
The Examiner has considered the Applicant’s arguments, but respectfully disagrees. The Examiner has considered the Applicants arguments, but respectfully disagrees. As shown in the restriction request issue on 07/08/26, Groups I, II and III represent different package structures; see previous restriction requirement for specific details. The Examiner further directs the Applicant to MPEP 35 U.S.C. 121, where a quote in the preceding section states that the Director may require restriction if two or more "independent and distinct" inventions that are claimed in one application. Furthermore, in 37 CFR 1.141, the statement is made that two or more "independent and distinct inventions" may not be claimed in one application. Because the Examiner has demonstrated in the previous restriction that Groups I, II and III have different structures that are not mutually shared, the Examiner takes the position that they represent different inventive entities; i.e. and therefore should be restricted. For these reasons, the Examiner takes the position that the restriction was proper and maintains his position.
For the above explained reasons, the Examiner maintains his position and therefore the restriction requirement is made final.
Claims #1-16 will be further Examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/05/24 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim #1, 2, 5-7, 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al., (U.S. Pub. No, 2023/0343749), hereinafter referred to as "Mao" and in view of Lee et al., (U.S. Pub. No. 2017/0358564), hereinafter referred to as "Lee".
Mao shows, with respect to claim #1, semiconductor package, comprising: a package substrate (fig. #2E, item 200) having a plurality of substrate pads (fig. #2E, item 212, 215, 218,) (paragraph 0017); a first semiconductor chip stacked (fig. #2D, item 216) (paragraph 0017-0018) on the package substrate (fig. #2L, item 233) (paragraph 0025), the first semiconductor chip (fig. #2D, item 216) (paragraph 0017) including a plurality of first chip pads (Below, fig. #Ex1, item FlP1), a plurality of first option pads (Below, fig. #Ex1, item OP1), a plurality of first sub-chip pads (Below, fig. #Ex1, item FSP1), and a plurality of first wirings (Below, fig. #Ex1, item 219a), the first chip pads (Below, fig. #Ex1, item FlP1) and the first option pads (Below, fig. #Ex1, item OP1) along a first horizontal direction (paragraph 0017, 0021), the first sub-chip pads (Below, fig. #Ex1, item FSP1) along a second horizontal direction perpendicular to the first horizontal direction, the first wirings electrically connecting the first chip pads and the first sub-chip pads to each other (paragraph 0030, 0043); a second semiconductor chip stacked (Below, fig. #Ex1, item SS1) the second semiconductor chip including a plurality of second chip pads (Below, fig. #Ex1, item SS1), a plurality of second option pads (Below, fig. #Ex1, item 2OP2), a plurality of second sub-chip pads (Below, fig. #Ex1, item SlP1) , and a plurality of second wirings (Below, fig. #Ex1, item 219a, 219, 206), the first chip pads and the second option pads along the first horizontal direction, the second sub-chip pads along the second horizontal direction, the second wirings electrically connecting the second chip pads and the second sub-chip pads to each other (paragraph 0021); and a plurality of connection lines electrically connecting the package substrate and the first and second semiconductor chips (paragraph 0030, 0043, 0043).
[AltContent: textbox (2nd level Optional Pads; 2OP2)][AltContent: ][AltContent: arrow][AltContent: oval][AltContent: arrow][AltContent: textbox (Second level Sub Pads; 2FSP2)][AltContent: textbox (Ex1)][AltContent: arrow][AltContent: arrow][AltContent: ][AltContent: oval][AltContent: arrow][AltContent: textbox (Second level Pads; SlP1)][AltContent: arrow][AltContent: textbox (Second Stack; SS1)][AltContent: textbox (219a)][AltContent: textbox (First level Sub Pads; FSP1)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (Optional Pads; OP1)][AltContent: textbox (First level Pads; FlP1)][AltContent: arrow][AltContent: arc]
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Mao substantially shows the claimed invention as shown in the rejection above.
Mao fails to show, with respect to claim #1, a semiconductor package comprising a second semiconductor chip stacked on the first semiconductor chip to cover the first sub-chip pads.
Lee teaches, with respect to claim #1, a semiconductor package comprising a second semiconductor chip stacked (fig. #1B, item S6) on the first semiconductor chip (fig. #1B, item S5) to cover the first sub-chip pads (paragraph 0039, 0064, 0069).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #1, to modified the invention of Mao as modified by the invention of Lee , which teaches, a semiconductor package comprising a second semiconductor chip stacked on the first semiconductor chip to cover the first sub-chip pads, to incorporate a structural condition that would large amount of electrical connections to various devices, as taught by Lee.
Mao shows, with respect to claim #2, semiconductor package, comprising: wherein the plurality of connection lines (Above, fig. #Ex1, item 219a, 219, 206) include: first conductive wires electrically connecting the plurality of substrate pads (fig. #2C, item 212, 215, 218) and the first chip pads; and second conductive wires electrically connecting the first chip pads and the second chip pads (paragraph 0021).
Mao shows, with respect to claim #5, semiconductor package, comprising: wherein the first conductive wires (Above, fig. #Ex1, item 219a, 219, 206) electrically connect the plurality of substrate pads (fig. #2C, item 212, 215, 218) and the first option pads, respectively, and the second conductive wires electrically connect the first option pads and the second option pads, respectively (paragraph 0021).
Mao shows, with respect to claim #6, semiconductor package, comprising wherein the first option pads and the second option pads (fig. #2C, item 212, 215, 218) receive data signals from the package substrate through the first and second conductive wires (Above, fig. #Ex1, item 219a, 219, 206) (paragraph 0021).
Mao shows, with respect to claim #7, semiconductor package, wherein the plurality of connection lines further include third conductive wires that electrically connect the plurality of substrate pads and the second sub-chip pads, respectively (Above, fig. #Ex1, item 219a, 219, 206) (paragraph 0021).
Mao fails to show, with respect to claim #9, a semiconductor package wherein the second semiconductor chip is stacked on the first semiconductor chip in a stepped shape in the second horizontal direction.
Lee teaches, with respect to claim #9, a semiconductor package wherein the second semiconductor chip (fig. #1B, item S6) is stacked on the first semiconductor chip (fig. #1B, item S5) in a stepped shape in the second horizontal direction (paragraph 0039, 0064, 0069).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #9, to modified the invention of Mao as modified by the invention of Lee , which teaches, a semiconductor package comprising a second semiconductor chip stacked on the first semiconductor chip to cover the first sub-chip pads, to incorporate a structural condition that would large amount of electrical connections to various devices, as taught by Lee.
Mao shows, with respect to claim #10, semiconductor package, comprising: wherein the first chip pads (Above, fig. #Ex1, item FlP1) are spaced apart from the second chip pads (Above, fig. #Ex1, item SlP1) in the second horizontal direction, and the first option pads (Above, fig. #Ex1, item OP1) are spaced apart from the second option pads (Above, fig. #Ex1, item 2OP2) in the second horizontal direction (paragraph 0030, 0043, 0043).
Mao shows, with respect to claim #11, semiconductor package, comprising: wherein the plurality of first sub-chip pads (Above, fig. #Ex1, item FSP1) are along a first side portion of the first semiconductor chip, the plurality of second sub-chip pads (Above, fig. #Ex1, item 2FSP2) are along a second side portion of the second semiconductor chip, and the first and second side portions are on a same plane (paragraph 0030, 0043, 0043).
Mao shows, with respect to claim #12, semiconductor package, comprising: wherein the first chip pads (Above, fig. #Ex1, item FlP1) and the first sub-chip pads (Above, fig. #Ex1, item FSP1) are on a first corner region of the first semiconductor chip, and the second chip pads (Above, fig. #Ex1, item SlP1) and the second sub-chip pads (Above, fig. #Ex1, item 2FSP2) are on a second corner region of the second semiconductor chip corresponding to the first corner region (paragraph 0030, 0043, 0043).
Mao shows, with respect to claim #13, wherein the first and second semiconductor chips are a same type of semiconductor device (paragraph 0027. 0040-0042).
Mao shows, with respect to claim #14 further comprising: a third semiconductor chip stacked (fig. #2D, item 216) on the second semiconductor chip (fig. #2D, item 213) to expose the second chip pads (fig. #2D, item 215), the second option pads (Above, fig. #Ex1, item OP1) and the second sub-chip pads (Above, fig. #Ex1, item FSP1), the third semiconductor chip including a plurality of third chip pads (fig. #2D, item 218) (paragraph 0017, 0018), a plurality of third sub-chip pads, and a plurality of third wirings (Above, fig. #Ex1, item 219a, 219, 206), the third chip pads along the first horizontal direction, the third sub-chip pads along the second horizontal direction, the third wirings electrically connecting the third chip pads and the third sub-chip pads to each other (paragraph 0021); and, the fourth semiconductor chip including a plurality of fourth chip pads, a plurality of fourth sub-chip pads, and plurality of fourth wirings, the fourth chip pads along the first horizontal direction, the fourth sub- chip pads along the second horizontal direction, the fourth wirings electrically connecting the fourth chip pads and the fourth sub-chip pads to each other, wherein the plurality of connection lines electrically connect the package substrate and the third and fourth semiconductor chips (paragraph 0030, 0043, 0043).
Mao substantially shows the claimed invention as shown in the rejection of claim #14 above.
Mao fails to show, with respect to claim #14, a semiconductor package comprising a fourth semiconductor chip stacked on the third semiconductor chip to cover the third sub-chip pads.
Lee teaches, with respect to claim #14, a semiconductor package comprising a fourth semiconductor chip stacked fig. #1B, item S6) on the third semiconductor chip (fig. #1B, item S5) to cover the third sub-chip pads(paragraph 0039, 0064, 0069).
The Examiner notes that, with respect to claim #14, Mao doses not explicitly state the presents of a fourth stack. However, the Examiner takes the position that Mao shows a process wherein multiple stacks may be added (paragraph 0015, 0025) and furthermore states that the process is yields non-limiting embodiments (abstract, paragraph 0003, 0010). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to continuously add additional stacks to fulfill the design needs of the device, since it has-been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Furthermore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #14, to modified the invention of Mao as modified by the invention of Lee , which teaches, a semiconductor package a fourth semiconductor chip stacked on the third semiconductor chip to cover the third sub-chip pads, to incorporate a structural condition that would large amount of electrical connections to various devices, as taught by Lee.
Mao shows, with respect to claim #15, a semiconductor package wherein the plurality of connection lines further include: fourth conductive wires (Above, fig. #Ex1, item 219a, 219, 206) electrically connecting the plurality of substrate pads and the third chip pads (fig. #2F, item 212, 215, 218), respectively (paragraph 0016-0017); fifth conductive wires electrically connecting the third chip pads and the fourth chip pads, respectively; and sixth conductive wires electrically connecting the plurality of substrate pads and the fourth sub-chip pads (paragraph 0021, 0030, 0043, 0043).
//
Claim #3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al., (U.S. Pub. No, 2023/0343749), hereinafter referred to as "Mao" as modified by Lee et al., (U.S. Pub. No. 2017/0358564), hereinafter referred to as "Lee" as shown in the rejection of claim #2 above and in further view of Chiu et al., (U.S. Pub. No. 2018/0005974), hereinafter referred to as "Chiu".
Mao as modified by Lee, substantially shows the claimed invention as shown in the rejection of claim #2 above.
Mao as modified by Lee, fails to show, with respect to claim #3, semiconductor package wherein the first chip pads and the second chip pads are configured to receive a power signal or a ground signal from the package substrate through the first and second conductive wires.
Chiu teaches, with respect to claim #3, a semiconductor package wherein the first chip pads and the second chip pads are configured to receive a power signal or a ground signal from the package substrate through the first and second conductive wires (paragraph 0050, 0058).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #3, to modified the invention of Mao as modified by Lee, with the modifications of Chiu’s invention, which teaches, a semiconductor package wherein the first chip pads and the second chip pads are configured to receive a power signal or a ground signal from the package substrate through the first and second conductive wires, to incorporate a structural condition that would allow control of operations within the device design, as taught by Chiu.
Mao as modified by Lee, fails to show, with respect to claim #4, semiconductor package wherein the first sub-chip pads are configured to receive the power signal or the ground signal from the first chip pads through the first wirings.
Chiu teaches, with respect to claim #4, a semiconductor package wherein the first sub-chip pads are configured to receive the power signal or the ground signal from the first chip pads through the first wirings (paragraph 0040, 0050, 0058).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #4, to modified the invention of Mao as modified by Lee, with the modifications of Chiu’s invention, which teaches, a semiconductor package wherein the first sub-chip pads are configured to receive the power signal or the ground signal from the first chip pads through the first wirings, to incorporate a structural condition that would allow control of operations within the device purpose, as taught by Chiu.
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Claim #8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al., (U.S. Pub. No, 2023/0343749), hereinafter referred to as "Mao" as modified by Lee et al., (U.S. Pub. No. 2017/0358564), hereinafter referred to as "Lee" as shown in the rejection of claim #7 above and in further view of Chiu et al., (U.S. Pub. No. 2018/0005974), hereinafter referred to as "Chiu".
Mao as modified by Lee, substantially shows the claimed invention as shown in the rejection of claim #7 above.
Mao as modified by Lee, fails to show, with respect to claim #8, semiconductor package wherein the second sub-chip pads are configured to transmit a power signal or a ground signal to the package substrate through the third conductive wires.
Chiu teaches, with respect to claim #8, a semiconductor package wherein the second sub-chip pads are configured to transmit a power signal or a ground signal to the package substrate through the third conductive wires (paragraph 0050, 0058).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #8, to modified the invention of Mao as modified by Lee, with the modifications of Chiu’s invention, which teaches, a semiconductor package wherein the second sub-chip pads are configured to transmit a power signal or a ground signal to the package substrate through the third conductive wires, to incorporate a structural condition that would allow control of operations within the device purpose, as taught by Chiu.
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Claim #16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al., (U.S. Pub. No, 2023/0343749), hereinafter referred to as "Mao" as modified by Lee et al., (U.S. Pub. No. 2017/0358564), hereinafter referred to as "Lee" as shown in the rejection of claim #15 above and in further view of Chiu et al., (U.S. Pub. No. 2018/0005974), hereinafter referred to as "Chiu".
Mao as modified by Lee, substantially shows the claimed invention as shown in the rejection of claim #15 above.
Mao as modified by Lee, fails to show, with respect to claim #16, semiconductor package wherein the third and fourth chip pads and the fourth sub-chip pads are configured to receive a power signal or a ground signal from the package substrate through the fourth to sixth conductive wires.
Chiu teaches, with respect to claim #16, a semiconductor package wherein the third and fourth chip pads and the fourth sub-chip pads are configured to receive a power signal or a ground signal from the package substrate through the fourth to sixth conductive wires (paragraph 0050, 0058).
The Examiner notes that, with respect to claim #16, Mao doses not explicitly state the presents of fourth to sixth conductive wires. However, the Examiner takes the position that Mao shows a process wherein multiple stacks wherein any pads may be wire connect to any chosen pad location (paragraph 0015, 0025) and furthermore states that the process is yields non-limiting embodiments (abstract, paragraph 0003, 0010). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to continuously add additional stacks to fulfill the design needs of the device, since it has-been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Furthermore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #16, to modified the invention of Mao as modified by Lee, with the modifications of Chiu’s invention, which teaches, a semiconductor package wherein the third and fourth chip pads and the fourth sub-chip pads are configured to receive a power signal or a ground signal from the package substrate through the fourth to sixth conductive wires, to incorporate a structural condition that would allow control of operations within the device design, as taught by Chiu.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
08/20/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights