DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR MEMORY DEVICES INCLUDING BACK-GATE ELECTRODES CONNECTED WITH A THROUGH-PLUG
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kim; Seung Hwan (US 2023/0207460; hereinafter Kim460).
Regarding claim 15, Kim460 discloses a semiconductor device, comprising:
a substrate (SUB; Figs 1,6-8; ¶ [0031]) including a memory cell region (CAR; Figs 5A-8; ¶ [0075]), a contact region (the portion of CTR starting with the nearest contact plug {WC/WC1-4} to CAR and extending away from CAR; Figs 5A-8; ¶ [0075]), and an interface region between the memory cell region and the contact region (the portion of CTR between CAR and the nearest contact plug WC; Figs 5A-7; ¶ [0075]);
stack structures extending in a first horizontal direction (D3; Figs 1-8) and spaced apart from each other in a second horizontal direction (D2; Figs 1-8) intersecting with the first horizontal direction (see, in particular WLS11,WLS12; Figs 5A,5B for the top-down configuration), the stack structures including first stack structures on the memory cell region (WLS/WLS11,WLS12 in CAR; Figs 3-8; ¶ [0075-76]) and second stack structures on the interface region and the contact region (WLS/WLS11,WLS12 in CTR; Figs 3-8; ¶ [0075-76])), the second stack structures electrically connected to the first stack structures (WLS extends through both first and second stack structures); and
through-plugs (WC/WC1-WC4; Figs 1,3,5A,6; ¶ [0031]) penetrating the stack structures in a vertical direction (D1; Figs 1-8),
wherein the first stack structures include,
gate electrodes (second word lines WL2; Figs 1-4,7-8; ¶ [0033]) extending in the first horizontal direction (D3) and stacked and spaced apart from each other in the vertical direction;
back-gate electrodes (first word lines WL1; Figs 1-4,7-8; ¶ [0033]) extending in the first horizontal direction between the gate electrodes and stacked and spaced apart from each other in the vertical direction; and
active layers (ACT; Figs 1-4,5B; ¶ [0033]) between the gate electrodes and the back-gate electrodes, the active layers including channel regions (CH; Fig 2; ¶ [0039]) extending in the second horizontal direction (D2) and overlapping the gate electrodes in the vertical direction, and
wherein the through-plugs (WC) are electrically connected to the back-gate electrodes (WL1, through WL2 and WLP; Fig 1; ¶ [0031,0059]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim; Seung Hwan (US 2023/0207460; hereinafter Kim460).
Regarding claim 16, Kim460 discloses a semiconductor device of claim 15, further comprising:
isolation layers (LSL/LSL1-LSL3; Fig 8; ¶ [0077]) in the memory cell region and between the first stack structures (WLS11,WLS12; Fig 8),
wherein each of the active layers includes a first source/drain region (SR; Fig 2; ¶ [0039]) and a second source/drain region (DR; Fig 2; ¶ [0039]); and,
a vertical conductive pattern (BL; Figs 2,5B; ¶ [0038]) electrically connected to the first source/drain region of one of the active layers and a capacitor structure (CAP; Figs 2,5B; ¶ [0038]) electrically connected to the second source/drain region of one of the active layers.
Kim 460 does not explicitly disclose each of the isolation layers (LSL) includes the vertical conductive, or the capacitor structure; however, it would have been obvious to a person having ordinary skill in the art to have placed BL and CAP in the isolation layers since active layers ACT and word lines WL are disclosed as being located between BL and CAP, and word lines stacks WLS1,WLS2 are described as being located between slits LSL; that is, BL and CAP and LSL are described as being in overlapping locations relative to the stack structures, and it would be obvious to satisfy the further limitations of claim 16 in order to maximize device density and reduce an area of the device, which is an ongoing goal known in the art.
Regarding claim 19, Kim460 discloses a semiconductor device of claim 15, but does not disclose wherein, in a plan view, the through-plugs are in a zigzag pattern in the second horizontal direction (D2); however, it would have been obvious to a person having ordinary skill in the art to have arranged the through-plugs in a zigzag pattern as a design choice since it has been held that such changes in shape/configuration are a matter of choice involving only routine skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See MPEP 2144.04.IV.B
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim; Seung Hwan (US 2023/0207460; hereinafter Kim460) in view of Kim; Seung Hwan (US 2022/0271040; hereinafter Kim040).
Regarding claim 17, Kim460 discloses a semiconductor device of claim 15, but does not disclose wherein the through-plugs penetrate through the second stack structures in the vertical direction on the interface region, and wherein the through-plugs are at both sides of each of the first stack structures.
In the same field of endeavor, Kim040 discloses a similar semiconductor device (Fig 1), which differs from the semiconductor device of Kim460 in that the gate electrodes (Kim040; WL; Fig 1; ¶ [0022]) and the back-gate electrodes (Kim040; BG; Fig 1; ¶ [0022]) of Kim040 are not connected to the same through-plugs as one another (Kim040; WL connected to WLP, BG connected to BGP; Fig 5; ¶ [0054]), each of WLP and BG are at both sides of similar stack structures comprising WL,ACT, and BG (Kim040; Fig 5), and WLP and BG are located at varying distances from the similar stack structures.
Accordingly, it would have been obvious to configure the semiconductor device of claim 15 in combination with that of Kim040 to arrive at the limitations of claim 17, the particular location of through-plugs connecting to each of back-gate electrodes and gate electrodes respectively being a matter of design choice to penetrate through the second stack structures in the vertical direction on the interface region. One would have had a reasonable expectation of success because of the similar structures of Kim460 and Kim040 in the similar endeavors. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). See MPEP 2144.04.E.C.
Regarding claim 18, Kim460 in view of Kim040 discloses a semiconductor device of claim 17, but does not disclose wherein the through-plugs partially overlap the second stack structures in the vertical direction; however, it would have been obvious to have configured the semiconductor device in this manner as a matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950). See MPEP 2144.04.E.C.
Allowable Subject Matter
Claims 1-14 and 20 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “back-gate electrodes extending between the gate electrodes in the first horizontal direction and stacked and spaced apart from each other in the vertical direction; and, a through-plug extending in the vertical direction and in contact with side surfaces of the back-gate electrodes”. That is, the prior art does not disclose one through-plug in contact with side surfaces of more than one back-gate electrode, in combination with the additional limitations of the claim.
Regarding claim 20, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “back-gate electrodes extending in the first horizontal direction between the gate electrodes and stacked and spaced apart from each other in the vertical direction” and “a through-plug extending in the vertical direction and in contact with side surfaces of the back-gate electrodes”. That is, the prior art does not disclose one through-plug in contact with side surfaces of more than one back-gate electrode, in combination with the additional limitations of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tang; Yi (US 2025/0324573; discloses a channel all around transistor including a back-gate electrically connected to a vertically oriented voltage regulation structure);
Kim; Seung Hwan (US 2022/0375853; the prior art discloses a semiconductor memory device including double word lines and cell isolation layers between word line stacks).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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