DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-10, 12-15 and 17-23 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (20190318990) in view of Shibayama (20210391671) further in view of Bai CN107393898
Regarding Claim 1, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses a package substrate, comprising: a substrate body, wherein the substrate body is provided with having a plurality of unit regions, wherein the a unit region, from the plurality of unit regions, comprises at least one solder ball group 3PD, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder 3PD ball that are arranged at spacings, Nakagawa fails to disclose the limitation where the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball. However, Shibayama discloses a differential pin pattern for a semiconductor device package where in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, and 0047-0049, the required parallelogram pattern is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required parallelogram pattern in Nakagawa as taught by Shibayama in order to reduce the crosstalk between adjacent solder balls.
Nakagawa and Shibayama combination fails to disclose the amended limitation with respect to the differential and single ended signal solder balls. However, Bai discloses a semiconductor packaging structure where in Figs. 2-4, elements 16/17 the required differential and single ended signal solder balls are disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required differential and single ended signal solder balls in Nakagawa and Shibayama combination as taught by Bai for semiconductor packaging structure of lower crosstalk issues.
Regarding Claim 3, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, Shibayama discloses inner angles of the parallelogram has inner angles 60°, 120°, 60°, and 120° respectively.
Regarding Claim 4, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, Shibayama discloses, wherein a ground solder ball is provided on a periphery of each-the at least one solder ball group
Regarding Claim 5, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024 Shibayama discloses the ground solder ball provided on the periphery of the at least one solder ball group comprises 12 ground solder balls, and the 12 ground solder balls are arranged in a hexagonal shape. Hexagonal shape is also could be drawn from Figs. 6 and 7 of Nagakawa.
Regarding Claim 6, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, Shibayama discloses, wherein the unit region comprises two solder ball groups sharing, and the two solder ball groups share a plurality of ground solder balls.
Regarding Claim 7, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024 Shibayama discloses, wherein the two solder ball groups of the unit region are arranged axisymmetrically or centrosymmetrically.
Regarding Claim 8, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, Shibayama discloses,
wherein two adjacent unit regions, from the plurality of unit regions, share a plurality of ground solder balls.
Regarding Claim 9, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses a semiconductor package, comprising a chip; and a package substrate, wherein the package substrate comprising: a substrate body having, wherein the substrate body is provided with a plurality of unit regions, wherein the a unit region, from the plurality of unit regions, comprises at least one solder ball group, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged at spacings, Nakagawa et al. fails to disclose the limitation where the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball,, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball, wherein the chip is disposed on the package substrate. However, Shibayama discloses a differential pin pattern for a semiconductor device package where in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, and 0047-0049, the required parallelogram pattern is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required parallelogram pattern in Nakagawa as taught by Shibayama in order to reduce the crosstalk between adjacent solder balls.
Nakagawa and Shibayama combination fails to disclose the amended limitation with respect to the differential and single ended signal solder balls. However, Bai discloses a semiconductor packaging structure where in Figs. 2-4, elements 16/17 the required differential and single ended signal solder balls are disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required differential and single ended signal solder balls in Nakagawa and Shibayama combination as taught by Bai for semiconductor packaging structure of lower crosstalk issues.
Regarding Claim 10, , in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses a circuit board; and a semiconductor package, comprising having a chip and a package substrate, wherein the package substrate comprising comprises a substrate body having, wherein the substrate body is provided with a plurality of unit regions, the a unit region, from the plurality of unit regions, comprises at least one solder ball group, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged at spacings. Nagakawa et al fails to disclose the limitation where the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball, wherein the chip is disposed on the package substrate, wherein the semiconductor package is disposed on the circuit board, and the semiconductor package is electrically connected to the circuit board. However, Shibayama discloses a differential pin pattern for a semiconductor device package where in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, and 0047-0049, the required parallelogram pattern is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required parallelogram pattern in Nakagawa as taught by Shibayama in order to reduce the crosstalk between adjacent solder balls.
Nakagawa and Shibayama combination fails to disclose the amended limitation with respect to the differential and single ended signal solder balls. However, Bai discloses a semiconductor packaging structure where in Figs. 2-4, elements 16/17 the required differential and single ended signal solder balls are disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required differential and single ended signal solder balls in Nakagawa and Shibayama combination as taught by Bai for semiconductor packaging structure of lower crosstalk issues.
Regarding Claim 12, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the parallelogram has inner angles of 60°, 120°, 60°, and 120° respectively.
Regarding Claim 13, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein a ground solder ball is provided on a periphery of the at least one solder ball group.
Regarding Claim 14, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, the ground solder ball provided on the periphery of the at least one solder ball group comprises round solder balls are arranged in a hexagonal shape. Hexagonal shape is also disclosed in Figs. 2A-2D and 8-10 of Shibayama et al.
Regarding Claim 15, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the unit region comprises two solder ball groups sharing a plurality of ground solder balls.
Regarding Claim 17, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, and 0047-0049 of Shibayama, wherein the parallelogram has inner angles of 60°, 120°, 60°, and 120° respectively.
Regarding Claim 18, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein a ground solder ball is provided on a periphery of the at least one solder ball group.
Regarding Claim 19, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the ground solder ball provided on the periphery of the at least one solder ball group comprises 12 ground solder balls are arranged in a hexagonal shape. Hexagonal shape is also disclosed in Figs. 2A-2D and 8-10 of Shibayama et al.
Regarding Claim 20, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the unit region comprises two solder ball groups sharing a plurality of ground solder balls.
Regarding Claim 21, Bai discloses a semiconductor packaging structure where in Figs. 2-4, elements 16/17 the required differential and single ended signal solder balls are disclosed.
Regarding Claim 22, Bai discloses a semiconductor packaging structure where in Figs. 2-4, elements 16/17 the required differential and single ended signal solder balls are disclosed.
Regarding Claim 23, Bai discloses a semiconductor packaging structure where in Figs. 2-4, elements 16/17 the required differential and single ended signal solder balls are disclosed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/27/2026
