CTNF 18/734,056 CTNF 79135 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-35 AIA Claim s 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1, 4-13 and 16-24 of copending Application No. 18/474,775 Although the claims at issue are not identical, they are not patentably distinct from each other because : Regarding Claim 1, both the instant claim 1 and claims 1, 4-13 and 16-24 of ‘775 recite a package substrate, comprising: a substrate body, wherein the substrate body is provided with having a plurality of unit regions, wherein the a unit region, from the plurality of unit regions, comprises at least one solder ball group, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged at spacings, wherein the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball. Regarding Claim 2, both the instant claim 2 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are single-ended signal solder balls, and the fifth solder ball and the sixth solder ball are differential signal solder balls. Regarding Claim 3, both the instant claim 3 and claims 1, 4-13 and 16-24 of ‘775 recite, inner angles of the parallelogram has inner angles 60°, 120°, 60°, and 120° respectively. Regarding Claim 4, both the instant claim 4 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein a ground solder ball is provided on a periphery of each-the at least one solder ball group . Regarding Claim 5, both the instant claim 5 and claims 1, 4-13 and 16-24 of ‘775 recite wherein the ground solder ball provided on the periphery of the at least one solder ball group comprises 12 ground solder balls, and the 12 ground solder balls are arranged in a hexagonal shape. Regarding Claim 6, both the instant claim 6 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the unit region comprises two solder ball groups sharing, and the two solder ball groups share a plurality of ground solder balls. Regarding Claim 7, both the instant claim 7 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the two solder ball groups of the unit region are arranged axisymmetrically or centrosymmetrically. Regarding Claim 8, both the instant claim 8 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein two adjacent unit regions, from the plurality of unit regions, share a plurality of ground solder balls. Regarding Claim 9, both the instant claim 9 and claims 1, 4-13 and 16-24 of ‘775 recite a semiconductor package, comprising a chip; and a package substrate, wherein the package substrate comprising: a substrate body having, wherein the substrate body is provided with a plurality of unit regions, wherein the a unit region, from the plurality of unit regions, comprises at least one solder ball group, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged at spacings, wherein the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball,, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball, wherein the chip is disposed on the package substrate. Regarding Claim 10, both the instant claim 10 and claims 1, 4-13 and 16-24 of ‘775 recite an electronic device, comprising a circuit board; and a semiconductor package, comprising having a chip and a package substrate, wherein the package substrate comprising comprises a substrate body having, wherein the substrate body is provided with a plurality of unit regions, the a unit region, from the plurality of unit regions, comprises at least one solder ball group, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged at spacings, wherein the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball,, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball, wherein the chip is disposed on the package substrate, wherein the semiconductor package is disposed on the circuit board, and the semiconductor package is electrically connected to the circuit board. Regarding Claim 11, both the instant claim 11 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are single-ended signal solder balls, and the fifth solder ball and the sixth solder ball are differential signal solder balls. Regarding Claim 12, both the instant claim 12 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the parallelogram has inner angles of 60°, 120°, 60°, and 120° respectively. Regarding Claim 13, both the instant claim 13 and claims 1, 4-13 and 16-24 of ‘775 recite wherein a ground solder ball is provided on a periphery of the at least one solder ball group. Regarding Claim 14, both the instant claim 14 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the ground solder ball provided on the periphery of the at least one solder ball group comprises round solder balls are arranged in a hexagonal shape. Regarding Claim 15, both the instant claim 15 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the unit region comprises two solder ball groups sharing a plurality of ground solder balls. Regarding Claim 16, both the instant claim 16 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are single-ended signal solder balls, and the fifth solder ball and the sixth solder ball are differential signal solder balls. Regarding Claim 17, both the instant claim 17 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the parallelogram has inner angles of 60°, 120°, 60°, and 120° respectively. Regarding Claim 18, both the instant claim 18 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein a ground solder ball is provided on a periphery of the at least one solder ball group. Regarding Claim 19, both the instant claim 19 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the ground solder ball provided on the periphery of the at least one solder ball group comprises 12 ground solder balls are arranged in a hexagonal shape. Regarding Claim 20, both the instant claim 20 and claims 1, 4-13 and 16-24 of ‘775 recite, wherein the unit region comprises two solder ball groups sharing a plurality of ground solder balls . This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa (20190318990) in view of Shibayama (20210391671) . Regarding Claim 1, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses a package substrate, comprising: a substrate body, wherein the substrate body is provided with having a plurality of unit regions, wherein the a unit region, from the plurality of unit regions, comprises at least one solder ball group 3PD, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder 3PD ball that are arranged at spacings, Nakagawa fails to disclose the limitation where the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball. However, Shibayama discloses a differential pin pattern for a semiconductor device package where in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, and 0047-0049, the required parallelogram pattern is disclosed. It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required parallelogram pattern in Nakagawa as taught by Shibayama in order to reduce the crosstalk between adjacent solder balls. Regarding Claim 2, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the first solder ball 3PD, the second solder ball 3PD, the third solder ball 3PD, and the fourth solder ball 3PD are single-ended signal solder balls, and the fifth solder ball 3PD and the sixth solder ball 3PD are differential signal solder balls. Regarding Claim 3, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, Shibayama discloses inner angles of the parallelogram has inner angles 60°, 120°, 60°, and 120° respectively. Regarding Claim 4, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, Shibayama discloses, wherein a ground solder ball is provided on a periphery of each-the at least one solder ball group Regarding Claim 5, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024 Shibayama discloses the ground solder ball provided on the periphery of the at least one solder ball group comprises 12 ground solder balls, and the 12 ground solder balls are arranged in a hexagonal shape. Hexagonal shape is also could be drawn from Figs. 6 and 7 of Nagakawa. Regarding Claim 6, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, Shibayama discloses, wherein the unit region comprises two solder ball groups sharing, and the two solder ball groups share a plurality of ground solder balls. Regarding Claim 7, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024 Shibayama discloses, wherein the two solder ball groups of the unit region are arranged axisymmetrically or centrosymmetrically. Regarding Claim 8, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, Shibayama discloses, wherein two adjacent unit regions, from the plurality of unit regions, share a plurality of ground solder balls. Regarding Claim 9, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses a semiconductor package, comprising a chip; and a package substrate, wherein the package substrate comprising: a substrate body having, wherein the substrate body is provided with a plurality of unit regions, wherein the a unit region, from the plurality of unit regions, comprises at least one solder ball group, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged at spacings, Nakagawa et al. fails to disclose the limitation where the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball,, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball, wherein the chip is disposed on the package substrate. However, Shibayama discloses a differential pin pattern for a semiconductor device package where in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, and 0047-0049, the required parallelogram pattern is disclosed. It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required parallelogram pattern in Nakagawa as taught by Shibayama in order to reduce the crosstalk between adjacent solder balls. Regarding Claim 10, , in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses a circuit board; and a semiconductor package, comprising having a chip and a package substrate, wherein the package substrate comprising comprises a substrate body having, wherein the substrate body is provided with a plurality of unit regions, the a unit region, from the plurality of unit regions, comprises at least one solder ball group, and the at least one solder ball group comprises a first solder ball, a second solder ball, a third solder ball, a fourth solder ball, a fifth solder ball, and a sixth solder ball that are arranged at spacings. Nagakawa et al fails to disclose the limitation where the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are respectively located at four vertices of a parallelogram, and the second solder ball and the third solder ball each are adjacent to the first solder ball, and the fifth solder ball is provided on a side of the parallelogram and the fifth solder ball is located between the first solder ball and the third solder ball, the sixth solder ball is provided on another side of the parallelogram and the sixth solder ball is located between the second solder ball and the fourth solder ball, and the first solder ball and the fourth solder ball are separately located on a perpendicular bisector of a connection line between the fifth solder ball and the sixth solder ball, wherein the chip is disposed on the package substrate, wherein the semiconductor package is disposed on the circuit board, and the semiconductor package is electrically connected to the circuit board. However, Shibayama discloses a differential pin pattern for a semiconductor device package where in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, and 0047-0049, the required parallelogram pattern is disclosed. It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required parallelogram pattern in Nakagawa as taught by Shibayama in order to reduce the crosstalk between adjacent solder balls. Regarding Claim 11, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses wherein the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are single-ended signal solder balls, and the fifth solder ball and the sixth solder ball are differential signal solder balls. Regarding Claim 12, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the parallelogram has inner angles of 60°, 120°, 60°, and 120° respectively. Regarding Claim 13, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein a ground solder ball is provided on a periphery of the at least one solder ball group. Regarding Claim 14, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, the ground solder ball provided on the periphery of the at least one solder ball group comprises round solder balls are arranged in a hexagonal shape. Hexagonal shape is also disclosed in Figs. 2A-2D and 8-10 of Shibayama et al. Regarding Claim 15, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the unit region comprises two solder ball groups sharing a plurality of ground solder balls. Regarding Claim 16, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the first solder ball, the second solder ball, the third solder ball, and the fourth solder ball are single-ended signal solder balls, and the fifth solder ball and the sixth solder ball are differential signal solder balls. Regarding Claim 17, in Figs 2A-2D and particularly 2D along with paragraphs 0031-0034, Figs. 8-10 and paragraphs 0017-0019, 0024, and 0047-0049 of Shibayama, wherein the parallelogram has inner angles of 60°, 120°, 60°, and 120° respectively. Regarding Claim 18, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein a ground solder ball is provided on a periphery of the at least one solder ball group. Regarding Claim 19, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the ground solder ball provided on the periphery of the at least one solder ball group comprises 12 ground solder balls are arranged in a hexagonal shape. Hexagonal shape is also disclosed in Figs. 2A-2D and 8-10 of Shibayama et al. Regarding Claim 20, in Figs 6 and 7 and paragraphs 0055, 0057, 0058, 0060, 0063-0068, 0070, 0071,0077, 0082, 0088, 0099, 0111,016,0124, 0157,0172, 0174, Nakagawa discloses, wherein the unit region comprises two solder ball groups sharing a plurality of ground solder balls. Examiner is including Zhao 20160181682 as pertinent prior art reference that is NOT relied upon on this rejection but that discloses parallelogram shaped pin structure for DDR connections in order to mitigate cross talk problem in high speed semiconductor device packages. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 6/11/2026 Application/Control Number: 18/734,056 Page 2 Art Unit: 2812 Application/Control Number: 18/734,056 Page 3 Art Unit: 2812 Application/Control Number: 18/734,056 Page 4 Art Unit: 2812 Application/Control Number: 18/734,056 Page 5 Art Unit: 2812 Application/Control Number: 18/734,056 Page 6 Art Unit: 2812 Application/Control Number: 18/734,056 Page 7 Art Unit: 2812 Application/Control Number: 18/734,056 Page 8 Art Unit: 2812 Application/Control Number: 18/734,056 Page 9 Art Unit: 2812 Application/Control Number: 18/734,056 Page 10 Art Unit: 2812 Application/Control Number: 18/734,056 Page 11 Art Unit: 2812 Application/Control Number: 18/734,056 Page 12 Art Unit: 2812 Application/Control Number: 18/734,056 Page 13 Art Unit: 2812 Application/Control Number: 18/734,056 Page 14 Art Unit: 2812
Prosecution Insights