DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of claims 1-16 in the reply filed on September 14, 2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (Xi, US 2022/0406664 A1).
Regarding claim 1, Xi shows a semiconductor device, comprising: a semiconductor substrate (substrate 102 in FIG. 13); a first nanosheet field effect transistor (FET) ( nanosheet transistor 108) disposed on the semiconductor substrate (substrate 108); a second nanosheet FET ( nanosheet 108 i.e. similar to instant application stack on sideways or nanosheet 108 comprises plurality sheets i.e. transistors ) stacked on the first nanosheet FET (nanosheet 108); dielectric material (dielectric 116 as shown in FIG. 2) vertically interposed between the first nanosheet FET and the second nanosheet FET (nanosheet 108); bottom source/drain (S/D) epitaxy contacting (S/D 128 in FIG. 9) nanosheets of the first nanosheet FET (nano sheet 108), the bottom S/D epitaxy being formed from depositional overgrowth, chemical mechanical polishing (CMP) and recession processes ( process limitations in product claim) and thereby comprising a flat upper surface coplanar with a portion of the dielectric material (see FIG. 9 128 surface with dielectric 116); and top S/D epitaxy (S/D 144) contacting nanosheets of the second nanosheet FET (nanosheet 108), the top S/D epitaxy being grown to have a shape differing from a shape of the bottom S/D epitaxy (wider E shape vs narrow U shape as shown in FIG. 13).
Regarding claim 2, Xi shows a semiconductor device, comprising, wherein the first nanosheet FET comprises inner spacers (spacer 116) through which the nanosheets of the first nanosheet FET are exposed to contact the bottom S/D epitaxy ( S/D 128).
Regarding claim 3, Xi shows a semiconductor device, further comprising dielectric liner material (spacer 116) and additional dielectric material (spacer 116) disposed on the flat upper surface of the bottom S/D epitaxy (S/D 128).
Regarding claim 4, Xi shows a semiconductor device, wherein the dielectric material, the dielectric liner material and the additional dielectric material differ ([0037]) from one another.
Regarding claim 5, Xi shows a semiconductor device, wherein the bottom S/D epitaxy is rectangular (128 as shown in FIG. 7), and the top S/D epitaxy is non-rectangular (see FIG. 12 with respect to FIG. 7).
Regarding claim 6, Xi shows a semiconductor device, wherein a side of the bottom S/D epitaxy ( S/D 128) is vertical and defines a vertical plane, and a side of the top S/D epitaxy (S/D 144), which corresponds to the side of the bottom S/D epitaxy, protrudes beyond the vertical plane (see FIG. 12).
Regarding claim 7, Xi shows a semiconductor device, wherein the bottom S/D epitaxy (S/D 128) is wider than a width of the nanosheets of the first nanosheet FET (see FIG. 12).
Regarding claim 8, Xi shows a semiconductor device, wherein the bottom S/D epitaxy (S/D 128) comprises the flat upper surface and a chamfered surface forming an obtuse angle with the flat upper surface, and the semiconductor device further comprises a wrap-around contact disposed in contact with the flat upper surface and the chamfered surface (see FIG. 12).
Regarding claim 9, Xi shows a semiconductor device, comprising: a semiconductor substrate (substrate 102); shallow trench isolation (STI) (STI 118) disposed in the semiconductor substrate (substrate 102); and first and second stacked nanosheet field effect transistors (FETs) (nanosheet 108) at opposite sides of the STI (STI 118) and each comprising a first nanosheet FET disposed on the semiconductor substrate (substrate 102); a second nanosheet FET stacked on the first nanosheet FET; dielectric material vertically (dielectric 116) interposed between the first nanosheet FET and the second nanosheet FET; bottom source/drain (S/D) epitaxy (S/D 128) contacting nanosheets of the first nanosheet FET, the bottom S/D epitaxy being formed from depositional overgrowth, chemical mechanical polishing (CMP) and recession processes and thereby comprising a flat upper surface coplanar (see FIG. 9 with respect to FIG. 12) with a portion of the dielectric material; and top S/D epitaxy contacting nanosheets of the second nanosheet FET, the top S/D epitaxy being grown to have a shape differing from a shape of the bottom S/D epitaxy (see FIG. 12).
Regarding claim 10, Xi shows a semiconductor device, comprising, wherein the first nanosheet FET of each of the first and second stacked nanosheet FETs comprises inner spacers (spacer 116) through which the nanosheets of the first nanosheet FET are exposed to contact the bottom S/D epitaxy (see FIG. 12).
Regarding claim 11, Xi shows a semiconductor device, comprising, further comprising dielectric liner material and additional dielectric material disposed on the flat upper surface of the bottom S/D epitaxy of each of the first and second stacked nanosheet FETs (see FIGs. 8-12).
Regarding claim 12, Xi shows a semiconductor device, comprising, further comprising, wherein, for each of the first and second stacked nanosheet FETs, the dielectric material, the dielectric liner material and the additional dielectric material differ from one another (see FIGs. 8-12).
Regarding claim 13, Xi shows a semiconductor device, comprising, further comprising, wherein the bottom S/D epitaxy is rectangular and the top S/D epitaxy is non-rectangular for each of the first and second stacked nanosheet FETs (see FIGs. 8-12).
Regarding claim 14, Xi shows a semiconductor device, comprising, further comprising, wherein, for each of the first and second stacked nanosheet FETs, a side of the bottom S/D epitaxy is vertical and defines a vertical plane extending upwardly from the STI (see FIGs. 8-12).
Regarding claim 15, Xi shows a semiconductor device, comprising, further comprising, wherein for each of the first and second stacked nanosheet FETs, the bottom S/D epitaxy is wider than a width of the nanosheets of the first nanosheet FET (see FIGs. 8-12).
Regarding claim 16, Xi shows a semiconductor device, comprising, further comprising, wherein for each of the first and second stacked nanosheet FETs the bottom S/D epitaxy comprises the flat upper surface and a chamfered surface remote from the STI and forming an obtuse angle with the flat upper surface, and the semiconductor device further comprises a wrap-around contact disposed in contact with the flat upper surface and the chamfered surface (see FIG. 8-12):
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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/ELIAS ULLAH/Primary Examiner, Art Unit 2893
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