Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 – 7, 9 - 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over WE (US 20240371737), in view of Lane (US 20240038831).
Regarding claim 1, WE discloses a semiconductor module, comprising:
a core (a core 102, Fig. 1);
a deep trench capacitor (DTC 106) within a DTC cavity (cavity 104) of the core;
ajinomoto build-up film (ABF filled the region 132, paragraph 31) filling spaces between the DTC and the core on the one or both sides of the DTC;
one or more upper metal layers (the patterned metallization layers 114) on an upper surface of the DTC and on an upper surface of the core;
one or more lower metal layers (the patterned metallization layers 124, 130) on a lower surface of the core; and
an upper dielectric layer (the dielectric layers 112) on an upper surface of the DTC (106) and on an upper surface the core (102), the upper PPG encapsulating sides of the one or more upper metal layers (118).
WE does not explicitly disclose the dielectric layer as a prepreg layer.
Lane suggests the layers (122a, 126a, paragraph 137, Fig. 16D; or layer 1520, paragraph 132) above and below the capacitor (106, Fig. 15D; or 506, Fig. 16D).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use a common insulator such as a prepreg in the circuit board in order to provide a solid substrate to mount components and traces to complete a circuit board.
Regarding claim 2, WE, in view of Lane, discloses the claimed invention as set forth in claim 1. WE further suggests terminals (terminal 110, Fig. 1) for the DTC are on the upper surface of the DTC.
Regarding claim 3, WE, in view of Lan, discloses the claimed invention as set forth in claim 1. Lane further suggests a lower PPG (126a, Fig. 16D) on a lower surface of the DTC and on the lower surface the core, the lower PPG encapsulating sides of the one or more lower metal layers (1503, Fig. 16B; 1527, Fig. 16D).
Regarding claim 4, WE, in view of Lane, discloses the claimed invention as set forth in claim 1. WE further suggests one or more thru-core connects (the plating side of the via 638, Fig. 6B) in one or more thru-core cavities (the cavity for the via 638 within the core 604) within the core, the one or more thru-core connects plating side surfaces of the one or more thru-core cavities (the via 638 has a plating layer for the side surfaces of the cavity) from the upper surface to the lower surface of the core, the one or more thru-core connects electrically coupling the one or more upper metal layers (640, 642) with the one or more lower metal layers; and one or more thru-core plugs (the plugging ink of the via 638; paragraph 54) filling remainder of the one or more thru-core cavities from the upper surface to the lower surface of the core.
Regarding claim 5, WE, in view of Lane, discloses the claimed invention as set forth in claim 4. WE further suggests the one or more thru-core connects are formed from metal (paragraph 50 or WE’s claim 14).
Regarding claim 6, WE, in view of Lane, discloses the claimed invention as set forth in claim 4. WE further suggests a thickness of the core is 400 μm or more (paragraph 92).
Regarding claim 7, WE, in view of Lane, discloses the claimed invention as set forth in claim 4. WE further suggests the one or more thru-core plugs are formed from materials different from the ABF material (the plug is made of ink; paragraph 54).
Regarding claim 9, WE, in view of Lane, discloses the claimed invention as set forth in claim 1. WE further suggests one or more thru-core vias (via 122, Fig. 1) within the core from the upper surface to the lower surface of the core, the one or more thru-core vias electrically coupling the one or more upper metal layers (118) with the one or more lower metal layers (124).
Regarding claim 10, WE, in view of Lane, discloses the claimed invention as set forth in claim 9. WE further suggests the one or more thru-core vias are formed from metal (paragraph 50 or WE’s claim 14).
Regarding claim 11, WE, in view of Lane, discloses the claimed invention as set forth in claim 9. WE further suggests a thickness of the core is 400 μm or more (paragraph 92).
Regarding claim 12, WE, in view of Lane, discloses the claimed invention as set forth in claim 1. WE further suggests the semiconductor module is incorporated into an apparatus selected from the group consisting of a music player (paragraph 85), a video player (paragraph 85), an entertainment unit, a navigation device (paragraph 85), a communications device, a mobile device, a mobile phone (paragraph 85), a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device (paragraph 85), a laptop computer (paragraph 85), a server, and a device in an automotive vehicle (paragraph 85).
Regarding claim 13, WE discloses a method of fabricating a semiconductor module, the method comprising:
providing a core (a core 102, Fig. 1);
forming a deep trench capacitor (DTC 106) within a DTC cavity (104) of the core;
filling spaces between the DTC and the core on the one or both sides of the DTC with ajinomoto build-up film (ABF fill in the region 132; paragraph 31);
forming one or more upper metal layers (114, 118) on an upper surface of the DTC and on an upper surface of the core (102);
forming one or more lower metal layers (124, 130) on a lower surface of the core; and
forming an upper insulator (112) on an upper surface of the DTC and on an upper surface the core, the upper PPG encapsulating sides of the one or more upper metal layers (118).
WE does not explicitly disclose the dielectric layer as a prepreg layer.
Lane suggests the layers (122a, 126a, paragraph 137, Fig. 16D; or layer 1520, paragraph 132) above and below the capacitor (106, Fig. 15D; or 506, Fig. 16D).
It would have been obvious to one having skill in the art at the effective filing date of the invention to use a common insulator such as a prepreg in the circuit board in order to provide a solid substrate to mount components and traces to complete a circuit board.
Regarding claim 14, WE, in view of Lane, discloses the claimed invention as set forth in claim 13. WE further suggests terminals (110) for the DTC are on the upper surface of the DTC.
Regarding claim 15, WE, in view of Lan, discloses the claimed invention as set forth in claim 13. Lane further suggests a lower PPG (126a, Fig. 16D) on a lower surface of the DTC and on the lower surface the core, the lower PPG encapsulating sides of the one or more lower metal layers (1503, Fig. 16B; 1527, Fig. 16D).
Regarding claim 16, WE, in view of Lane, discloses the claimed invention as set forth in claim 13. WE further suggests forming one or more thru-core connects (the plating side of the via 638, Fig. 6B) in one or more thru-core cavities (the cavity for the via 638 within the core 604) within the core, the one or more thru-core connects plating side surfaces of the one or more thru-core cavities (the via 638 has a plating layer for the side surfaces of the cavity) from the upper surface to the lower surface of the core, the one or more thru-core connects electrically coupling the one or more upper metal layers (640, 642) with the one or more lower metal layers; and one or more thru-core plugs (the plugging ink of the via 638; paragraph 54) filling remainder of the one or more thru-core cavities from the upper surface to the lower surface of the core.
Regarding claim 17, WE, in view of Lane, discloses the claimed invention as set forth in claim 16. WE further suggests the one or more thru-core connects are formed from metal (paragraph 50 or WE’s claim 14).
Regarding claim 18, WE, in view of Lane, discloses the claimed invention as set forth in claim 13. WE further suggests one or more thru-core vias (via 122, Fig. 1) within the core from the upper surface to the lower surface of the core, the one or more thru-core vias electrically coupling the one or more upper metal layers (118) with the one or more lower metal layers (124).
Regarding claim 19, WE, in view of Lane, discloses the claimed invention as set forth in claim 18. WE further suggests the one or more thru-core vias are formed from metal (paragraph 50 or WE’s claim 14).
Regarding claim 20, WE, in view of Lane, discloses the claimed invention as set forth in claim 13. WE further suggests fabricating the semiconductor module comprises: drilling the core to form one or more thru-core cavities (form the cavity in the core 404, Fig. 4B); plating (plating the sides such as of the through hole for the via) sides of the one or more thru-core cavities with metal to form one or more thru-core connects (Fig. 4B); plugging remainder of the one or more thru-core cavities with one or more thru-core plugs (the plug via with inks; paragraph 54); plating the upper surface of the core with at least one upper metal layer of the one or more upper metal layers (432, 436); forming a DTC cavity (forming cavity 418) within the core; applying a PL tape lamination on the upper surface of the core (using Pl tape 510, paragraph 49); forming the DTC (402 or 524) within the DTC cavity; filling the spaces between the DTC and the core on the one or both sides of the DTC with the ABF (444; the filling dielectric is ABF, paragraph 31); removing the PL tape lamination (remove tape 510); and forming the upper PPG on an upper surface of the DTC and on the upper surface the core (Lane suggests forming prepreg layers 122a and 126a on top and bottom surface of the core).
Claim(s) 8, is/are rejected under 35 U.S.C. 103 as being unpatentable over WE (US 20240371737), in view of Lane (US 20240038831), in further view of Sundaram (US 20230067888).
Regarding claim 8, WE, in view of Lane, discloses the claimed invention as set forth in claim 4.
WE does not explicitly disclose the one or more thru-core plugs are formed from the ABF material.
Sundaram teaches the via (1346, Fig. 12) is filled with ABF material (paragraph 120).
It would have been obvious to one having skill in the art at the effective filing date of the invention to fill the through hole via with a common material in this field such as ABF in order to plug the hole and providing reinforcement for the circuit substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mohammadighaleni (US 20250218962) discloses a core having an embedded deep trench capacitor, Fig. 22.
Hsu (US 20230062775) discloses a core having an embedded deep trench capacitor, Fig. 1K.
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/BINH B TRAN/Primary Examiner, Art Unit 2848