CTNF 18/734,462 CTNF 87259 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-20 of U.S. Patent No. 12,035,581 . Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent ‘581 contain all limitations of the claims of the current Application. The independent claims are shown below for reference . Current Application Patent 12,035,581 1. A display panel, comprising a base, a functional film layer arranged on the base, a plurality of first light-emitting elements arranged at a side of the functional film layer distal to the base, and a plurality of subpixel regions arranged in an array form, wherein the functional film layer comprises a power source signal line layer, a data line layer and a compensation functional layer, the power source signal line layer comprises a power source signal line pattern arranged at each subpixel region, the data line layer comprises a data line pattern arranged at each subpixel region, the power source signal line pattern comprises a first portion extending in a first direction, the data line pattern extends in the first direction, and the compensation functional layer comprises a compensation functional pattern arranged at at least one subpixel region; each of the first light-emitting elements comprises a first anode, a first light-emitting pattern and a first cathode sequentially laminated in a direction away from the base; an orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding power source signal line pattern onto the base at a first overlapping region, the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding data line pattern onto the base at a second overlapping region, and the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding compensation functional pattern onto the base at a third overlapping region; wherein in a direction perpendicular to the base, a difference between a thickness of the compensation functional layer and a thickness of the power source signal line layer is within a threshold range, or a difference between the thickness of the compensation functional layer and a thickness of the data line layer is within a threshold range. 1. A display panel, comprising a base, a functional film layer arranged on the base, a plurality of first light-emitting elements arranged at a side of the functional film layer distal to the base, and a plurality of subpixel regions arranged in an array form, wherein the functional film layer comprises a power source signal line layer, a data line layer and a compensation functional layer, the power source signal line layer comprises a power source signal line pattern arranged at each subpixel region, the data line layer comprises a data line pattern arranged at each subpixel region, the power source signal line pattern comprises a first portion extending in a first direction, the data line pattern extends in the first direction, and the compensation functional layer comprises a compensation functional pattern arranged at at least one subpixel region; each of the first light-emitting elements comprises a first anode, a first light-emitting pattern and a first cathode sequentially laminated in a direction away from the base; an orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding power source signal line pattern onto the base at a first overlapping region, the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding data line pattern onto the base at a second overlapping region, and the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding compensation functional pattern onto the base at a third overlapping region; and the second overlapping region is arranged between the first overlapping region and the third overlapping region, wherein in a direction perpendicular to the base, a difference between a thickness of the compensation functional layer and a thickness of the power source signal line layer is within a threshold range, or a difference between the thickness of the compensation functional layer and a thickness of the data line layer is within a threshold range. 18 . A display panel, comprising a base, a functional film layer arranged on the base, a plurality of first light-emitting elements arranged at a side of the functional film layer distal to the base, and a plurality of subpixel regions arranged in an array form, wherein the functional film layer comprises a power source signal line layer, a data line layer and a compensation functional layer, the power source signal line layer comprises a power source signal line pattern arranged at each subpixel region, the data line layer comprises a data line pattern arranged at each subpixel region, the power source signal line pattern comprises a first portion extending in a first direction, the data line pattern extends in the first direction, and the compensation functional layer comprises a compensation functional pattern arranged at at least one subpixel region; each of the first light-emitting elements comprises a first anode, a first light-emitting pattern and a first cathode sequentially laminated in a direction away from the base; an orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding power source signal line pattern onto the base at a first overlapping region, the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding data line pattern onto the base at a second overlapping region, and the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding compensation functional pattern onto the base at a third overlapping region; wherein the display panel further comprises a plurality of subpixel driving circuitries, wherein a first part of the subpixel driving circuitries correspond to the first light-emitting elements respectively, each of the first part of the subpixel driving circuitries is configured to drive a corresponding first light-emitting element to emit light; the subpixel driving circuitry comprises a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor; a gate electrode of the first transistor is coupled to a corresponding gate scanning line pattern, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, and a second electrode of the first transistor is coupled to a gate electrode of the driving transistor; a gate electrode of the second transistor is coupled to a corresponding resetting signal line pattern, a first electrode of the second transistor is coupled to a corresponding initialization signal line pattern, and a second electrode of the second transistor is coupled to the gate electrode of the driving transistor; a gate electrode of the fourth transistor is coupled to the corresponding gate scanning line pattern, a first electrode of the fourth transistor is coupled to a corresponding data line pattern, and a second electrode of the fourth transistor is coupled to a first electrode of the driving transistor; the first electrode of the driving transistor is coupled to a corresponding power source signal line pattern, and the second electrode of the driving transistor is coupled to a corresponding first light-emitting element; a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor, and a second electrode plate of the storage capacitor is coupled to the corresponding power source signal line pattern, wherein each of the orthogonal projection of the first electrode plate of the storage capacitor onto the base and the orthogonal projection of the second electrode plate of the storage capacitor onto the base partially overlaps the orthogonal projection of the corresponding first anode onto the base. 11. A display panel, comprising a base, a functional film layer arranged on the base, a plurality of first light-emitting elements arranged at a side of the functional film layer distal to the base, and a plurality of subpixel regions arranged in an array form, wherein the functional film layer comprises a power source signal line layer, a data line layer and a compensation functional layer, the power source signal line layer comprises a power source signal line pattern arranged at each subpixel region, the data line layer comprises a data line pattern arranged at each subpixel region, the power source signal line pattern comprises a first portion extending in a first direction, the data line pattern extends in the first direction, and the compensation functional layer comprises a compensation functional pattern arranged at at least one subpixel region; each of the first light-emitting elements comprises a first anode, a first light-emitting pattern and a first cathode sequentially laminated in a direction away from the base; an orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding power source signal line pattern onto the base at a first overlapping region, the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding data line pattern onto the base at a second overlapping region, and the orthogonal projection of the first anode onto the base overlaps an orthogonal projection of a corresponding compensation functional pattern onto the base at a third overlapping region; and the second overlapping region is arranged between the first overlapping region and the third overlapping region, wherein in a direction perpendicular to the base, a difference between a thickness of the compensation functional layer and a thickness of the power source signal line layer is within a threshold range, or a difference between the thickness of the compensation functional layer and a thickness of the data line layer is within a threshold range. comprising a plurality of subpixel driving circuitries, wherein a first part of the subpixel driving circuitries correspond to the first light-emitting elements respectively, each of the first part of the subpixel driving circuitries is configured to drive a corresponding first light-emitting element to emit light; the subpixel driving circuitry comprises a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor; a gate electrode of the first transistor is coupled to a corresponding gate scanning line pattern, a first electrode of the first transistor is coupled to a second electrode of the driving transistor, and a second electrode of the first transistor is coupled to a gate electrode of the driving transistor; a gate electrode of the second transistor is coupled to a corresponding resetting signal line pattern, a first electrode of the second transistor is coupled to a corresponding initialization signal line pattern, and a second electrode of the second transistor is coupled to the gate electrode of the driving transistor; a gate electrode of the fourth transistor is coupled to the corresponding gate scanning line pattern, a first electrode of the fourth transistor is coupled to a corresponding data line pattern, and a second electrode of the fourth transistor is coupled to a first electrode of the driving transistor; the first electrode of the driving transistor is coupled to a corresponding power source signal line pattern, and the second electrode of the driving transistor is coupled to a corresponding first light-emitting element; a first electrode plate of the storage capacitor is coupled to the gate electrode of the driving transistor, and a second electrode plate of the storage capacitor is coupled to the corresponding power source signal line pattern. the display panel further comprises a third metal layer, the first conductive connection member is arranged at the third metal layer, and an orthogonal projection of the first conductive connection member in the first part of the subpixel driving circuitries onto the base does not overlap the orthogonal projection of the first anode corresponding to the first conductive connection member onto the base. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM C TRAPANESE whose telephone number is (571)270-3304. The examiner can normally be reached Monday - Friday 7am-12pm & 8pm-10pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812 Application/Control Number: 18/734,462 Page 2 Art Unit: 2812 Application/Control Number: 18/734,462 Page 3 Art Unit: 2812 Application/Control Number: 18/734,462 Page 4 Art Unit: 2812 Application/Control Number: 18/734,462 Page 5 Art Unit: 2812 Application/Control Number: 18/734,462 Page 6 Art Unit: 2812 Application/Control Number: 18/734,462 Page 7 Art Unit: 2812 Application/Control Number: 18/734,462 Page 8 Art Unit: 2812
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