Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 06/05/24. Claims 1-27 are pending in this application. Applicants have elected claims 1-9 and 19-27 for examination. Non-elected claims 10-18 are withdrawn from examination.
Information Disclosure Statement
The information disclosure statements filed on 10/30/24, 05/20/26 and 09/30/26 have been received and are being considered.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8 and 9 are rejected under 35 U.S.C. §103 as being unpatentable over Mun (US 20220165658 A1) and further in view of Pandit (US 20220375898 A1).
Regarding claim 1, Mun discloses an assembly comprising:
a substrate having a major surface (see 102 having a surface);
alternating inter-metal dielectric (IMD) layers and metal layers above the major surface of the substrate (see 150, 152, 156, 158, etc);
a first capacitor having a first plate 162 formed in a first one of the metal layers and a second plate formed in a second one of the metal layers 110; and
However, mun does not explicitly disclose a second capacitor having a third plate formed in a third one of the metal layers and a fourth plate formed in a fourth one of the metal layers; wherein the first capacitor is electrically coupled to the second capacitor.
However, Pandit is directed towards 3-d stacked devices and at least at fig 1b, Pandit discloses a second capacitor having a third plate 108, formed in a third one of the metal layers and a fourth plate formed in a fourth one of the metal layers 152; wherein the first capacitor is electrically coupled to the second capacitor (see abstract where IC couples the first and second capacitor).
Mun and Pandit are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Mun and Pandit. Mun and Pandit may be combined by forming the device of Mun to have two capacitors, as taught in Pandit. One having ordinary skill in the art would be motivated to combine Mun and Pandit in order to create a compact 3D device.
Regarding claim 8, Mun, Pandit disclose the assembly of claim 1 wherein the first plate is configured for high voltage and the fourth plate is configured for low voltage (Intended use, this office action notes that these are Mun and Pandit disclose low voltage-configured Mim capacitors).
Regarding claim 9, Mun Pandit disclose the assembly of claim 1 wherein the first and second capacitors are configured to isolate a high voltage circuit from a low voltage circuit (Intended use, this office action notes that these are Mun and Pandit disclose voltage-configured Mim capacitors that may be configured to hold higher voltage).
Claims 19, 26, 27 are rejected under 35 U.S.C. §103 as being unpatentable over Neuman (US 20240114696 A1), Mun (US 20220165658 A1) and further in view of Pandit (US 20220375898 A1).
Regarding claim 19, Neumann discloses an integrated circuit comprising:
a first semiconductor die comprising a receiver circuit (see fig. 6);
a second semiconductor die comprising a transmitter circuit (see fig 6 disclosing transmitter circuit); and
a third semiconductor die comprising an isolator circuit structure (see fig 6, disclosing isolator), wherein the isolator circuit structure (see para [0088] and fig 5)includes:
Mun discloses a substrate having a major surface (see 102 having a surface);
alternating inter-metal dielectric (IMD) layers and metal layers above the major surface of the substrate (see 150, 152, 156, 158, etc);
a first capacitor having a first plate 162 formed in a first one of the metal layers and a second plate formed in a second one of the metal layers 110; and
However, mun does not explicitly disclose a second capacitor having a third plate formed in a third one of the metal layers and a fourth plate formed in a fourth one of the metal layers; wherein the first capacitor is electrically coupled to the second capacitor.
However, Pandit is directed towards 3-d stacked devices and at least at fig 1b, Pandit discloses a second capacitor having a third plate 108, formed in a third one of the metal layers and a fourth plate formed in a fourth one of the metal layers 152; wherein the first capacitor is electrically coupled to the second capacitor (see abstract where IC couples the first and second capacitor).
Neuman, Mun and Pandit are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Neuman, Mun and Pandit. Neuman, Mun and Pandit may be combined by forming the device of Neuman and Mun to have two capacitors, as taught in Pandit. One having ordinary skill in the art would be motivated to combine Neumann, Mun and Pandit in order to create a compact 3D device.
Regarding claim 26, Neuman, Mun and Pandit disclose the circuit of claim 19 wherein the first plate is configured for high voltage and the fourth plate is configured for low voltage(Intended use, this office action notes that these are Mun and Pandit disclose low voltage-configured Mim capacitors).
Regarding claim 27, Neuman, Mun and Pandit disclose the circuit of claim 19 wherein the first and second capacitors are configured to isolate a high voltage circuit from a low voltage circuit(Intended use, this office action notes that these are Mun and Pandit disclose voltage-configured Mim capacitors that may be configured to hold higher voltage).
Claims 2-7are rejected under 35 U.S.C. §103 as being unpatentable over Mun (US 20220165658 A1) and Pandit (US 20220375898 A1) and further in view of Hsu (US 20220367610 A1).
Regarding claim 2, Mun and Pandit disclose the assembly of claim 1, but do not explicitly disclose wherein the first capacitor and the second capacitor are electrically coupled in series.
However, Hsu, at least at figs 1-5 discloses a Mim capacitor wherein the first capacitor and the second capacitor are electrically coupled in series (see 120/140/160).
Mun ,Pandit, and Hsu are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Mun and Pandit with Hsu. Mun and Pandit may be combined with Hsu by forming the metal layers in accordance with the arrangement disclosed in Hsu. One having ordinary skill in the art would be motivated to combine Mun and Pandit with Hsu in order to form a Mim Capacitor.
Regarding claim 3, Mun, Pandit, and Hsu disclose the assembly of claim 2 wherein the second plate of the first capacitor is electrically coupled to the third plate of the second capacitor (see 509).
Regarding claim 4, Mun, Pandit and Hsu disclose the assembly of claim 1 wherein the second plate of the first capacitor and the third plate of the second capacitor are configured to reduce a parasitic capacitance with the substrate (intended use, this office action notes that the Mim capacitors are arranged on and above the substrate, there by reducing distance between capacitor and substrate, minimizing parasitic capacitance).
Regarding claim 5, Mun, Pandit and Hsu disclose the assembly of claim 4 wherein the first, second, third, and fourth plates are configured to increase a breakdown voltage of the first capacitor and the second capacitor(intended use, this office action notes that the Mim capacitors are arranged on and above each other, increasing capacitance without reducing dialectic thickness, there by increasing breakdown voltage).
Regarding claim 6, Mun and Pandit disclose the assembly of claim 1 Hsu further discloses wherein the first and second plates are vertically aligned with respect to the major surface of the substrate (see figs 1-5 disclosing vertical alignment of capacitor plates).
Mun ,Pandit, and Hsu are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Mun and Pandit with Hsu. Mun and Pandit may be combined with Hsu by forming the metal layers in accordance with the arrangement disclosed in Hsu. One having ordinary skill in the art would be motivated to combine Mun and Pandit with Hsu in order to form a Mim Capacitor.
Regarding claim 7, Hsu and Pandit disclose he assembly of claim 1 Hsu wherein the third and fourth plates are vertically aligned with respect to the major surface of the substrate, see figs 1-5.
Mun ,Pandit, and Hsu are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Mun and Pandit with Hsu. Mun and Pandit may be combined with Hsu by forming the metal layers in accordance with the arrangement disclosed in Hsu. One having ordinary skill in the art would be motivated to combine Mun and Pandit with Hsu in order to form a Mim Capacitor.
Claims 20-25 are rejected under 35 U.S.C. §103 as being unpatentable over Neuman (US 20240114696 A1), Mun (US 20220165658 A1) and Pandit (US 20220375898 A1) and further in view of Hsu (US 20220367610 A1).
Regarding claim 20, Neuman, Mun and Pandit disclose the circuit of claim 19, Hsu further discloses wherein the first capacitor and the second capacitor are electrically coupled in series (see figs 2-5 of Hsu).
Neuman, Mun ,Pandit, and Hsu are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Neuman, Mun and Pandit with Hsu. Neuman, Mun and Pandit may be combined with Hsu by forming the metal layers in accordance with the arrangement disclosed in Hsu. One having ordinary skill in the art would be motivated to combine Neuman, Mun and Pandit with Hsu in order to form a Mim Capacitor.
Regarding claim 21, Neuman, Mun ,Pandit, disclose the circuit of claim 19 wherein the second plate of the first capacitor is electrically coupled to the third plate of the second capacitor(see figs 2-5 of Hsu).
Neuman, Mun ,Pandit, and Hsu are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Neuman, Mun and Pandit with Hsu. Neuman, Mun and Pandit may be combined with Hsu by forming the metal layers in accordance with the arrangement disclosed in Hsu. One having ordinary skill in the art would be motivated to combine Neuman, Mun and Pandit with Hsu in order to form a Mim Capacitor.
Regarding claim 22, Neuman, Mun, Pandit and Hsu disclose the circuit of claim 19 wherein the second plate of the first capacitor and the fourth plate of the second capacitor are configured to reduce a parasitic capacitance with the substrate(intended use, this office action notes that the Mim capacitors are arranged on and above the substrate, there by reducing distance between capacitor and substrate, minimizing parasitic capacitance).
Regarding claim 23, Neuman, Mun, Pandit and Hsu disclose the circuit of claim 22 wherein the first, second, third and fourth plates are configured to increase a breakdown voltage of the first capacitor and the second capacitor(intended use, this office action notes that the Mim capacitors are arranged on and above each other, increasing capacitance without reducing dialectic thickness, there by increasing breakdown voltage).
Regarding claim 24, Neuman, Mun, Pandit, and Hsu disclose the circuit of claim 19 wherein the first and second plates are vertically aligned with respect to the major surface of the substrate Hsu further discloses wherein the first and second plates are vertically aligned with respect to the major surface of the substrate (see figs 1-5 disclosing vertical alignment of capacitor plates).
Neuman, Mun ,Pandit, and Hsu are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Neuman, Mun and Pandit with Hsu. Neuman, Mun and Pandit may be combined with Hsu by forming the metal layers in accordance with the arrangement disclosed in Hsu. One having ordinary skill in the art would be motivated to combine Neuman, Mun and Pandit with Hsu in order to form a Mim Capacitor.
Regarding claim 25, Neuman, Mun and Pandit and Hsu disclose the circuit of claim 19 wherein Hsu discloses the third and fourth plates are vertically aligned with respect to the major surface of the substrate, see figs 1-5.
Neuman, Mun ,Pandit, and Hsu are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Neuman, Mun and Pandit with Hsu. Neuman, Mun and Pandit may be combined with Hsu by forming the metal layers in accordance with the arrangement disclosed in Hsu. One having ordinary skill in the art would be motivated to combine Neuman, Mun and Pandit with Hsu in order to form a Mim Capacitor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
