Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 5, 8 – 9, 11, 13 – 14, 18, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ross ( Pat. No. 2791760 ), hereinafter Ross.
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Regarding Independent Claim 1, Ross teaches a structure comprising:
a lateral bipolar ( Ross, FIG. 1, 12, n-p-n, 13, 14; column 2, line 39, The body 12, as shown in Fig. 1, contains two n-p junctions 13 and 14 in back-to-back relationship ) transistor; and
a ferroelectric ( Ross, FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 and applying signals to the ferroelectric to establish a charge upon its surface ) switching element electrically coupled to the lateral bipolar ( Ross, FIG. 1, 12, n-p-n, 13, 14 ) transistor.
Regarding Claim 2, Ross teaches the structure as claimed in claim 1, on which this claim is dependent, Ross further teaches:
wherein the ferroelectric ( Ross, FIG. 1, 22 ) switching element contacts ( Ross, column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 ) an underlying semiconductor substrate of the lateral bipolar ( Ross, FIG. 1, 12, n-p-n, 13, 14 ) transistor.
Regarding Claim 3, Ross teaches the structure as claimed in claim 1, on which this claim is dependent, Ross further teaches:
wherein the lateral bipolar ( Ross, FIG. 1, 12, n-p-n, 13, 14 ) transistor comprises: a base ( Ross, FIG. 1, 18 ) region; a collector ( Ross, FIG. 1, 17 ) region adjacent to the base region; and an emitter ( Ross, FIG. 1, 19 ) region adjacent to the collector ( Ross, FIG. 1, 17 ) region.
Regarding Claim 5, Ross teaches the structure as claimed in claim 3, on which this claim is dependent, Ross further teaches:
wherein the ferroelectric ( Ross, FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 ) switching element is between the collector ( Ross, FIG. 1, 17 ) region and the emitter ( Ross, FIG. 1, 19 ) region.
Regarding Claim 8, Ross teaches the structure as claimed in claim 1, on which this claim is dependent, Ross further teaches:
wherein the ferroelectric ( Ross, FIG. 1, 22 ) switching element comprises ferroelectric material and a metal ( Ross, FIG. 1, 23; column 4, line 7, second electrode 23 as the plates of a condenser while the ferroelectric body 22 is positioned ) material over the ferroelectric ( Ross, FIG. 1, 22 ) material.
Regarding Claim 9, Ross teaches the structure as claimed in claim 8, on which this claim is dependent, Ross further teaches:
wherein the ferroelectric ( Ross, FIG. 1, 22 ) material comprises a single layer of ferroelectric ( Ross, FIG. 1, 22 ) material.
Regarding Claim 11, Ross teaches the structure as claimed in claim 8, on which this claim is dependent, Ross further teaches:
further comprising a contact ( Ross, FIG. 1, 23; column 4, line 7, second electrode 23 ) to independently supply voltage ( Ross, FIG. 1, 25, 26; column 4, line 8, ferroelectric body 22 is positioned therebetween and applying a signal to input terminals 25 and 26 connected to electrodes 23 and 21 ) to the ferroelectric ( Ross, FIG. 1, 22 ) material.
Regarding Independent Claim 13, Ross teaches a structure comprising:
a lateral bipolar ( Ross, FIG. 1, 12, n-p-n, 13, 14; column 2, line 39, The body 12, as shown in Fig. 1, contains two n-p junctions 13 and 14 in back-to-back relationship ) transistor comprising:
a first diffusion region ( Ross, FIG. 1, 18; n-type region );
a second diffusion region ( Ross, FIG. 1, 17; p-type region ) adjacent to the first diffusion region ( Ross, FIG. 1, 18; n-type region ); and
a third diffusion region ( Ross, FIG. 1, 19; n-type region ) adjacent to the second diffusion region ( Ross, FIG. 1, 17; p-type region );
an independently controlled ferroelectric ( Ross, FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 and applying signals to the ferroelectric to establish a charge upon its surface ) material between the second diffusion region ( Ross, FIG. 1, 17; p-type region ) and the third diffusion region ( Ross, FIG. 1, 19; n-type region ); and
a contact ( Ross, FIG. 1, 23; column 4, line 7, second electrode 23 as the plates of a condenser while the ferroelectric body 22 is positioned ) electrically coupled to the ferroelectric ( Ross, FIG. 1, 22 ) material.
Regarding Claim 14, Ross teaches the structure as claimed in claim 13, on which this claim is dependent, Ross further teaches:
wherein the ferroelectric ( Ross, FIG. 1, 22 ) material is electrically ( Ross, FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 and applying signals to the ferroelectric to establish a charge upon its surface ) coupled to the lateral bipolar ( Ross, FIG. 1, 12, n-p-n, 13, 14 ) transistor.
Regarding Claim 18, Ross teaches the structure as claimed in claim 13, on which this claim is dependent, Ross further teaches:
further comprising metal ( Ross, FIG. 1, 23; column 4, line 7, second electrode 23 as the plates of a condenser while the ferroelectric body 22 is positioned ) material over the ferroelectric ( Ross, FIG. 1, 22 ) material and the contact ( Ross, FIG. 1, 23; column 4, line 7, second electrode 23 ) independently supplies voltage ( Ross, FIG. 1, 25, 26; column 4, line 8, ferroelectric body 22 is positioned therebetween and applying a signal to input terminals 25 and 26 connected to electrodes 23 and 21 ) to the ferroelectric ( Ross, FIG. 1, 22 ) material.
Regarding Independent Claim 20, Ross teaches a method comprising:
forming a lateral bipolar ( Ross, FIG. 1, 12, n-p-n, 13, 14; column 2, line 39, The body 12, as shown in Fig. 1, contains two n-p junctions 13 and 14 in back-to-back relationship ) transistor; and
forming a ferroelectric ( Ross, FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 and applying signals to the ferroelectric to establish a charge upon its surface ) switching element electrically coupled to the lateral bipolar ( Ross, FIG. 1, 12, n-p-n, 13, 14 ) transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7, 12, 15, 17, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ross, in view of Ko ( Pub. No. 20140124871 A1 ), herein after Ko.
Regarding Claim 4, Ross teaches the structure as claimed in claim 3, on which this claim is dependent, Ross further teaches:
wherein the base region ( Ross, FIG. 1, 18 ) the collector ( Ross, FIG. 1, 17 ) region and the collector region ( Ross, FIG. 1, 17 ) the emitter region ( Ross, FIG. 1, 19 ).
Ross fails to disclose:
wherein the base region surrounds the collector region and the collector region surrounds the emitter region.
However, Ko teaches:
wherein the base region surrounds the collector region and the collector region surrounds the emitter region ( Ko, FIG. 2, 101, 102, 103; [0020], A base region 102 underlying an annular polysilicon gate 104 is disposed about a periphery of the emitter region 101 … An annular P+ doping region 103 that functions as a collector region of the lateral PNP bipolar transistor 1 is formed within the N well 14 and is disposed about a periphery of the base region 102 ).
Ross and Ko are both considered to be analogous to the claimed invention because they are forming lateral bipolar transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( a ferroelectric switching element electrically coupled to the lateral bipolar transistor ), to incorporate the teachings of Ko ( base, emitter, and collector are annularly arranged ), to implement that wherein the base region surrounds the collector region and the collector region surrounds the emitter region. Doing so would make the lateral bipolar junction transistors to be formed using a CMOS compatible process, and therefore a CMOS-based lateral bipolar junction transistor (lateral BJT) with high beta can be implemented.
Regarding Claim 7, Ross teaches the structure as claimed in claim 1, on which this claim is dependent, Ross further teaches:
wherein the ferroelectric ( Ross, FIG. 1, 22 ) switching element sits on a semiconductor substrate.
Ross fails to disclose:
wherein the ferroelectric switching element sits on a well in a semiconductor substrate.
However, Ko teaches:
wherein a well in a semiconductor substrate (FIG. 2, 14; [0019], The lateral PNP bipolar transistor 1 comprises a P+ doping region 101 that functions as an emitter region of the lateral PNP bipolar transistor 1, which is formed within an N well (NW) 14).
Ross and Ko are both considered to be analogous to the claimed invention because they are forming lateral bipolar transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 ), to incorporate the teachings of Ko ( FIG. 2, 14; [0019], The lateral PNP bipolar transistor 1 comprises a P+ doping region 101 that functions as an emitter region of the lateral PNP bipolar transistor 1, which is formed within an N well (NW) 14 ), to implement that mounting ferro-electric body to a surface including the region bounded by n-p junctions to make the ferroelectric switching element sits on a well in a semiconductor substrate. Doing so would make a PNP or NPN lateral bipolar junction transistor on which a ferro-electric body is mounted.
Regarding Claim 12, Ross teaches the structure as claimed in claim 11, on which this claim is dependent,
Ross fails to disclose:
further comprising a logic device on a same semiconductor substrate as the ferroelectric material.
However, Ko teaches:
further comprising a logic device on a same semiconductor substrate as the ferroelectric material ( Ko, [0006], The integration of CMOS transistors with bipolar transistors to provide Bipolar-CMOS (BiCMOS) integrated circuits is now well established. BiCMOS circuits provide advantages such as high speed, high drive, mixed voltage performance with analog-digital capabilities, which are beneficial in applications such as telecommunications … fabricate an integrated circuit combining both bipolar transistors and field effect transistors on the same chip; [0021], According to the present invention, the N well 14, the emitter region 101, the collector region 103, the STI region 150, the N+ well pickup region 160 and the polysilicon gate 104 may be formed with the formation of respective diffusion regions and gate of CMOS devices. The polysilicon gate 104 serves as an implant blockout mask during the formation of the emitter region 101 and the collector region 103 ).
Ross and Ko are both considered to be analogous to the claimed invention because they are forming lateral bipolar transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 ), to incorporate the teachings of Ko ( [0006], Bipolar-CMOS (BiCMOS) integrated circuits; [0021], Bipolar device formed with CMOS device ), to implement that further comprising a logic device on a same semiconductor substrate as the ferroelectric material. Doing so would make BiCMOS circuits provide advantages such as high speed, high drive, mixed voltage performance with analog-digital capabilities, which are beneficial in applications such as telecommunications.
Regarding Claim 15, Ross teaches the structure as claimed in claim 13, on which this claim is dependent, Ross further teaches:
wherein the base region ( Ross, FIG. 1, 18 ) the collector ( Ross, FIG. 1, 17 ) region and the collector ( Ross, FIG. 1, 17 ) region the emitter region ( Ross, FIG. 1, 19 ).
Ross fails to disclose:
wherein the base region surrounds the collector region and the collector region surrounds the emitter region.
However, Ko teaches:
wherein the base region surrounds the collector region and the collector region surrounds the emitter region ( Ko, FIG. 2, 101, 102, 103; [0020], A base region 102 underlying an annular polysilicon gate 104 is disposed about a periphery of the emitter region 101 … An annular P+ doping region 103 that functions as a collector region of the lateral PNP bipolar transistor 1 is formed within the N well 14 and is disposed about a periphery of the base region 102 ).
Ross and Ko are both considered to be analogous to the claimed invention because they are forming lateral bipolar transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( a ferroelectric switching element electrically coupled to the lateral bipolar transistor ), to incorporate the teachings of Ko ( base, emitter, and collector are annularly arranged ), to implement that wherein the base region surrounds the collector region and the collector region surrounds the emitter region. Doing so would make the lateral bipolar junction transistors to be formed using a CMOS compatible process, and therefore a CMOS-based lateral bipolar junction transistor (lateral BJT) with high beta can be implemented.
Regarding Claim 17, Ross teaches the structure as claimed in claim 13, on which this claim is dependent,
Ross fails to disclose:
wherein the ferroelectric switching element sits on a well in a semiconductor substrate.
However, Ko teaches:
wherein a well in a semiconductor substrate (FIG. 2, 14; [0019], The lateral PNP bipolar transistor 1 comprises a P+ doping region 101 that functions as an emitter region of the lateral PNP bipolar transistor 1, which is formed within an N well (NW) 14).
Ross and Ko are both considered to be analogous to the claimed invention because they are forming lateral bipolar transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 ), to incorporate the teachings of Ko ( FIG. 2, 14; [0019], The lateral PNP bipolar transistor 1 comprises a P+ doping region 101 that functions as an emitter region of the lateral PNP bipolar transistor 1, which is formed within an N well (NW) 14 ), to implement that mounting ferro-electric body to a surface including the region bounded by n-p junctions to make the ferroelectric switching element sits on a well in a semiconductor substrate. Doing so would make a PNP or NPN lateral bipolar junction transistor on which a ferro-electric body is mounted.
Regarding Claim 19, Ross teaches the structure as claimed in claim 13, on which this claim is dependent,
Ross fails to disclose:
further comprising a logic device on a same semiconductor substrate as the ferroelectric material.
However, Ko teaches:
further comprising a logic device on a same semiconductor substrate as the ferroelectric material ( Ko, [0006], The integration of CMOS transistors with bipolar transistors to provide Bipolar-CMOS (BiCMOS) integrated circuits is now well established. BiCMOS circuits provide advantages such as high speed, high drive, mixed voltage performance with analog-digital capabilities, which are beneficial in applications such as telecommunications … fabricate an integrated circuit combining both bipolar transistors and field effect transistors on the same chip; [0021], According to the present invention, the N well 14, the emitter region 101, the collector region 103, the STI region 150, the N+ well pickup region 160 and the polysilicon gate 104 may be formed with the formation of respective diffusion regions and gate of CMOS devices. The polysilicon gate 104 serves as an implant blockout mask during the formation of the emitter region 101 and the collector region 103 ).
Ross and Ko are both considered to be analogous to the claimed invention because they are forming lateral bipolar transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( FIG. 1, 22; column 3, line 68, mounting a ferro-electric body 22 in proximity to a surface of the body including a portion of the region bounded by n-p junctions 13 and 14 ), to incorporate the teachings of Ko ( [0006], Bipolar-CMOS (BiCMOS) integrated circuits; [0021], Bipolar device formed with CMOS device ), to implement that further comprising a logic device on a same semiconductor substrate as the ferroelectric material. Doing so would make BiCMOS circuits provide advantages such as high speed, high drive, mixed voltage performance with analog-digital capabilities, which are beneficial in applications such as telecommunications.
Claims 6, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ross, in view of Singh ( Pub. No. 20230061717 A1 ), herein after Singh.
Regarding Claim 6, Ross teaches the structure as claimed in claim 3, on which this claim is dependent,
Ross fails to disclose:
further comprising a shallow trench isolation structure isolating the base region and the collector region.
However, Singh teaches:
further comprising a shallow trench isolation structure isolating the base region and the collector region ( Singh, FIG. 6, 14, 28, 30; [0024], the shallow trench isolation structure 14 between the collector region 28 and extrinsic base region 30 ).
Ross and Singh are both considered to be analogous to the claimed invention because they are forming lateral bipolar transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( a ferroelectric switching element electrically coupled to the lateral bipolar transistor ), to incorporate the teachings of Singh ( [0024], the shallow trench isolation structure 14 between the collector region 28 and extrinsic base region 30 ), to implement that further comprising a shallow trench isolation structure isolating the base region and the collector region. Doing so would provide a lateral bipolar transistor with the collector region extending within a semiconductor substrate below shallow trench isolation structures, and therefore the lateral bipolar transistor provided for high voltage RF device applications (e.g., low noise amplifiers and power amplifiers) can be implemented.
Regarding Claim 16, Ross teaches the structure as claimed in claim 13, on which this claim is dependent, Ross further teaches:
the ferroelectric ( Ross, FIG. 1, 22 ) material surrounds the emitter region ( Ross, FIG. 1, 19 ).
Ross fails to disclose:
further comprising a shallow trench isolation structure isolating the base region and the collector region,
However, Singh teaches:
further comprising a shallow trench isolation structure isolating the base region and the collector region ( Singh, FIG. 6, 14, 28, 30; [0024], the shallow trench isolation structure 14 between the collector region 28 and extrinsic base region 30 ).
Ross and Singh are both considered to be analogous to the claimed invention because they are forming lateral bipolar transistors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( a ferroelectric switching element electrically coupled to the lateral bipolar transistor ), to incorporate the teachings of Singh ( [0024], the shallow trench isolation structure 14 between the collector region 28 and extrinsic base region 30 ), to implement that further comprising a shallow trench isolation structure isolating the base region and the collector region. Doing so would provide a lateral bipolar transistor with the collector region extending within a semiconductor substrate below shallow trench isolation structures, and therefore the lateral bipolar transistor provided for high voltage RF device applications (e.g., low noise amplifiers and power amplifiers) can be implemented.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ross, in view of Duncombe ( Pat. No. 6172385 B1 ), herein after Duncombe.
Regarding Claim 10, Ross teaches the structure as claimed in claim 8, on which this claim is dependent,
Ross fails to disclose:
wherein the ferroelectric material comprises multiple layers of ferroelectric material.
However, Duncombe teaches:
wherein the ferroelectric material comprises multiple layers of ferroelectric material ( Duncombe, column 3, line 13, a multilayer ferroelectric film 18 composed of two different ferroelectric materials and/or more than one composition of ferroelectric material (denoted as 18A and 18B, respectively) ).
Ross and Duncombe are both considered to be analogous to the claimed invention because they are forming ferroelectric material. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ross ( a ferroelectric switching element electrically coupled to the lateral bipolar transistor ), to incorporate the teachings of Duncombe ( a multilayer ferroelectric film composed of two different ferroelectric materials ), to implement that wherein the ferroelectric material comprises multiple layers of ferroelectric material. Doing so would provide a multilayer ferroelectric structure coupled to the lateral bipolar transistor, and therefore a multilayer ferroelectric structure which has reduced leakage current and improved microstructural porosity better than a single layer ferroelectric films can be implemented.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is (703)756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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