DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 8 – 14, 17, and 19 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2009/0224391).
Regarding claim 1, Lin teaches (FIG. 8G):
A semiconductor package, comprising:
a lower redistribution wiring layer (88) having a first region and a second region, and including first redistribution wirings (90);
a semiconductor chip (102) on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings (104/94);
a molding member (106) covering the semiconductor chip on the lower redistribution wiring layer;
a plurality of vertical conductive structures (94) penetrating the molding member on the second region of the lower redistribution wiring layer, each of the plurality of vertical conductive structures including a first conductive pillar (94) on a bonding pad on the first redistribution wirings in the second region and a second conductive pillar (100) stacked on the first conductive pillar; and
an upper redistribution wiring layer (110) on the molding member and having second redistribution wirings (108) electrically connected to the plurality of vertical conductive structures, wherein the second redistribution wirings include, a first upper redistribution wiring extending from an end portion of the second conductive pillar on an upper molding member (FIG. 8G); and
a second upper redistribution wiring (112) stacked on the first upper redistribution wiring.
Regarding claim 2, Lin teaches:
The semiconductor package of claim 1, wherein each of the first conductive pillars has a first length and each of the second conductive pillars has a second length greater than the first length (FIG. 8G).
Regarding claim 5, Lin teaches:
The semiconductor package of claim 1, wherein each of the first conductive pillars has a first diameter and each of the second conductive pillars has a second diameter different from the first diameter (FIG. 12).
Regarding claim 6, Lin teaches:
The semiconductor package of claim 1, wherein the upper redistribution wiring layer further includes a heat dissipation pattern on a backside surface of the semiconductor chip (FIG. 7, claim 23).
Regarding claim 8, Lin teaches (FIG. 7):
The semiconductor package of claim 6, wherein the heat dissipation pattern directly contacts the backside surface of the semiconductor chip.
Regarding claim 9, Lin teaches (FIG. 8G):
The semiconductor package of claim 1, wherein the semiconductor chip is arranged such that a front surface on which chip pads are arranged faces the lower redistribution wiring layer, and the semiconductor chip is mounted on the lower redistribution wiring layer via conductive bumps (104/94) that are on the chip pads.
Regarding claim 10, Lin teaches:
The semiconductor package of claim 1, further comprising: a second package on the upper redistribution wiring layer, wherein the second package includes a package substrate and at least one second semiconductor chip stacked on the package substrate (102).
Regarding claim 11, Lin teaches (FIG. 12):
A semiconductor package, comprising:
a lower redistribution wiring layer (88) having a first region and a second region surrounding the first region, the lower redistribution wiring layer including first redistribution wirings (86);
a plurality of first and second bonding pads (90) on an uppermost redistribution wirings of the first redistribution wirings on an upper surface of the lower redistribution wiring layer, the plurality of first bonding pads arranged in the first region, the plurality of second bonding pads arranged in the second region (FIG. 12);
a semiconductor chip (102) mounted on the first region of the lower redistribution wiring layer such that a front surface on which chip pads are arranged faces the lower redistribution wiring layer, the semiconductor chip electrically connected to the first redistribution wirings (104/94);
a molding member (106) covering the semiconductor chip on the lower redistribution wiring layer;
a plurality of vertical conductive structures penetrating the molding member on the second region of the lower redistribution wiring layer, the plurality of vertical conductive structures including first conductive pillars (94) on the plurality of second bonding pads and second conductive pillars (100) stacked on the first conductive pillars respectively; and
an upper redistribution wiring layer (110) on the molding member, having second redistribution wirings (108) electrically connected to the plurality of vertical conductive structures, and a heat dissipation pattern (FIG. 7, claim 23) on a backside surface of the semiconductor chip.
Regarding claim 12, Lin teaches:
The semiconductor package of claim 11, wherein the semiconductor chip is mounted on the lower redistribution wiring layer via conductive bumps (94) that are on the chip pads.
Regarding claim 13, Lin teaches (FIG. 12):
The semiconductor package of claim 12, wherein the conductive bumps are on the plurality of first bonding pads respectively.
Regarding claim 14, Lin teaches (FIG. 12):
The semiconductor package of claim 11, wherein each of the first conductive pillars has a first length and each of the second conductive pillars has a second length greater than the first length.
Regarding claim 17, Lin teaches:
The semiconductor package of claim 11, wherein the second redistribution wirings includes: a first upper redistribution wiring (108) extending from an end portion of the second conductive pillar on an upper molding member; and a second upper redistribution wiring (112) stacked on the first upper redistribution wiring.
Regarding claim 19, Lin teaches (FIG. 7):
The semiconductor package of claim 11, wherein the heat dissipation pattern directly contacts the backside surface of the semiconductor chip.
Regarding claim 20, Lin teaches (FIG. 12):
A semiconductor package, comprising:
a lower redistribution wiring layer (88) having a first region and a second region surrounding the first region, the lower redistribution wiring layer including first redistribution wirings (86);
a semiconductor chip (102) on the first region of the lower redistribution wiring layer such that a front surface on which chip pads are arranged faces the lower redistribution wiring layer (FIG. 12);
a molding member (106) covering the semiconductor chip on the lower redistribution wiring layer;
a plurality of vertical conductive structures penetrating the molding member on the second region of the lower redistribution wiring layer, the plurality of vertical conductive structures electrically connected to the first redistribution wirings, each of the plurality of vertical conductive structures including a first conductive pillar (94) and a second conductive pillar (100) stacked on the first conductive pillar; and
an upper redistribution wiring layer (110) on the molding member, having second redistribution wirings (108) electrically connected to the plurality of vertical conductive structures, and a heat dissipation pattern (FIG. 7, claim 23) on a backside surface of the semiconductor chip, wherein each of the first conductive pillars has a first length and each of the second conductive pillars has a second length greater than the first length (FIG. 12).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2009/0224391).
Regarding claim 3, Lin teaches varying the heights of the first and second portions of the conductive pillars (FIG. 8G – 12), but fails to expressly disclose:
The semiconductor package of claim 2, wherein the first length is in a range of 50 μm to 100 μm, and the second length is in a range of 200 μm to 300 μm.
However, it would have been an obvious matter of design choice to make the different portions of the conductive through pillar of whatever relative sizes were desired, since such a modification would have involved a mere change in the proportions of components. A change in proportion is generally recognized as being within the level of ordinary skill in the art. In re Reese, 129 USPQ 402. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 4, Lin teaches varying the heights of the first and second portions of the conductive pillars (FIG. 8G – 12), but fails to expressly disclose:
The semiconductor package of claim 2, wherein the second length of the second conductive pillar is at least twice the first length of the first conductive pillar.
However, it would have been an obvious matter of design choice to make the different portions of the conductive through pillar of whatever relative sizes were desired, since such a modification would have involved a mere change in the proportions of components. A change in proportion is generally recognized as being within the level of ordinary skill in the art. In re Reese, 129 USPQ 402. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 15, Lin teaches varying the heights of the first and second portions of the conductive pillars (FIG. 8G – 12), but fails to expressly disclose:
The semiconductor package according to claim 14, wherein the first length is in a range of 50 μm to 100 μm, and the second length is in a range of 200 μm to 300 μm.
However, it would have been an obvious matter of design choice to make the different portions of the conductive through pillar of whatever relative sizes were desired, since such a modification would have involved a mere change in the proportions of components. A change in proportion is generally recognized as being within the level of ordinary skill in the art. In re Reese, 129 USPQ 402. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 16, Lin teaches varying the heights of the first and second portions of the conductive pillars (FIG. 8G – 12), but fails to expressly disclose:
The semiconductor package of claim 14, wherein the second length of the second conductive pillar is at least twice the first length of the first conductive pillar.
However, it would have been an obvious matter of design choice to make the different portions of the conductive through pillar of whatever relative sizes were desired, since such a modification would have involved a mere change in the proportions of components. A change in proportion is generally recognized as being within the level of ordinary skill in the art. In re Reese, 129 USPQ 402. Further, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 7 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2009/0224391) as applied to claims 6 and 17 above, and further in view of Lin2 et al. (US 2010/0140772).
Regarding claim 7, Lin teaches including a heat spreader directly attached to the backside of the package (FIG. 7, claim 23, [0044]), but fails to expressly disclose:
The semiconductor package of claim 6, wherein the first upper redistribution wiring and the heat dissipation pattern include a same metal material.
However, Lin2 (FIG. 7), teaches an embedded device package structure having heat sink portion 130c/126f formed of the same material as the RDL wiring layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the heat sink structure of Lin2 formed at the same time and using the same materials as the RDL wiring layer of the device to enable the heat sink structure of Lin in a conventional consolidated manner to improve device manufacturability.
Regarding claim 18, Lin teaches including a heat spreader directly attached to the backside of the package (FIG. 7, claim 23, [0044]), but fails to expressly disclose:
The semiconductor package of claim 17, wherein an upper surface of the first upper redistribution wiring is located on a same plane as an upper surface of the heat dissipation pattern.
However, Lin2 (FIG. 7), teaches an embedded device package structure having heat sink portion 130c/126f formed of the same material as the RDL wiring layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the heat sink structure of Lin2 formed at the same time and using the same materials as the RDL wiring layer of the device to enable the heat sink structure of Lin in a conventional consolidated manner to improve device manufacturability.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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/CORY W ESKRIDGE/ Primary Examiner, Art Unit 3624
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