DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of U.S. Patent No. 11,955,452. Although the claims at issue are not identical, they are not patentably distinct from each other because they overlap in scope as indicated below (cited patent is referenced below in Bold with Claim in parenthesis).
Claim 1:
A semiconductor device comprising:
a supporting substrate including a first conductive part that includes a first obverse surface facing a first side in a thickness direction and is located on a first side in a first direction orthogonal to the thickness direction, and a second conductive part that includes a second obverse surface facing the first side in the thickness direction and is located on a second side in the first direction;
A semiconductor module comprising: a conductive substrate having an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction (Claim 1)
a plurality of first semiconductor elements mounted on the first conductive part and each having a switching function;
a plurality of second semiconductor elements mounted on the second conductive part and each having a switching function;
at least one semiconductor element electrically bonded to the obverse surface and having a switching function (Claim 1)
the at least one semiconductor element includes a plurality of first semiconductor elements electrically bonded to the first conductive portion, and a plurality of second semiconductor elements electrically bonded to the second conductive portion (Claim 1)
a first terminal protruding to the first side in the first direction from the first conductive part;
a first input terminal and a second input terminal that are offset in one sense of a first direction relative to the conductive substrate, the first direction being perpendicular to the thickness direction; and at least one output terminal offset in another sense of the first direction relative to the conductive substrate (Claim 1)
a first conductive member electrically connecting the plurality of first semiconductor elements and the second conductive part;
the at least one semiconductor element includes a plurality of first semiconductor elements electrically bonded to the first conductive portion, and a plurality of second semiconductor elements electrically bonded to the second conductive portion (Claim 1)
a second conductive member electrically connecting the plurality of second semiconductor elements and the first terminal; and
the first input terminal is electrically connected to the first conductive portion, the second input terminal has an opposite polarity to the first input terminal, the output terminal is electrically connected to the second conductive portion, the conducting member includes a first conducting member connected to the plurality of first semiconductor elements and the second conductive portion, and a second conducting member connected to the plurality of second semiconductor elements and the second input terminal, the semiconductor module further comprising a control terminal connected to one of the plurality of first semiconductor elements and the plurality of second semiconductor elements, and the control terminal is arranged on the obverse surface and extends along the thickness direction (Claim 1)
a sealing resin covering the plurality of first semiconductor elements, the plurality of second semiconductor elements, the first conductive member, the second conductive member, a portion of the supporting substrate, and a portion of the first terminal,
a sealing resin covering at least a part of the first conductive portion, at least a part of the second conductive portion, the plurality of first semiconductor elements, the plurality of second semiconductor elements, the first conducting member, and the second conducting member (Claim 4)
wherein the second conductive member is connected to the supporting substrate.
a second conducting member connected to the plurality of second semiconductor elements and the second input terminal (Claim 1)
Allowable Subject Matter
Claims 2-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertaining to claim 2, the prior art does not teach nor suggest wherein the first conductive part includes a plurality of first bonding parts bonded to the plurality of first semiconductor elements, and a second bonding part bonded to the second conductive member, the second conductive member includes a plurality of third bonding parts bonded to the plurality of second semiconductor elements, a fourth bonding part bonded to the first terminal, and a first path part interposed between the plurality of third bonding parts and the fourth bonding part, and the first path part is connected to the supporting substrate.
Claims 3-17 all depend from Claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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