DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment
Acknowledgment is made of applicant's Amendment, filed 02-26-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 3 has/have been amended, and claim(s) 1-22 remain(s) pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim(s) 3 recite(s) the language (emphasis added) “the second memory cell is on at least one of a common wordline as the first memory cell, and on a common bitline as the first memory cell”, where the specification does not define a first or second memory as group of programmable devices, but rather as a single programable device connected a single wordline and a single bitline, as depicted in figure 3. A person of ordinary skill in the art would understand when a memory cell is connected on the common wordline and the common bitline as another memory cell, the memory cell and the another memory are the same memory cell, and the disclosure does not support this limitation. The limitation would overcome the 112 rejection if rewritten (emphasis added) --the second memory cell is on at least one of a same wordline as the first memory cell, or on a same bitline as the first memory cell--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 7, 11, 12, 14, 20, and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ha, US 20200066342 A1.
As to claim 1, Ha discloses a system (see Ha Fig 1) comprising:
a memory array (see Ha Fig 1 Ref NVM) comprising at least one first memory cell (see Ha Fig 8 Refs most right MC and WL5); and
a controller (see Ha Fig 1 Ref 100) configured to: determine errors (see Ha Fig 11 Ref S114) associated with the first memory cell; determine a physical address of at least one second memory cell (see Ha Fig 8 Refs most right MC and WL6; OR see annotated image of Ha Fig 8 below) using at least one offset (see Ha Fig 11 Ref S119) from a physical address of the first memory cell (see Ha Fig 8 Refs most right MC and WL5; OR see annotated image of Ha Fig 8 below); and
apply a write refresh to the second memory cell (see Ha Fig 11 Ref S116).
As to claim 2, Ha discloses the system of claim 1, wherein
the at least one first memory cell is at least one of an individual memory cell (see Ha Fig 8 Refs most right MC and WL5), and a plurality of cells (see Ha Fig 8 Ref WL5) associated with a memory unit of the memory array.
As to claim 3, Ha discloses the system of claim 1, wherein
the second memory cell is on at least one of a common wordline as the first memory cell, and on a common bitline as the first memory cell (see annotated image of Ha Fig 8 below).
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As to claim 4, Ha discloses the system of claim 1, wherein
the controller is further configured to determine at least one temperature (see Ha Fig 6 Ref L1 and Para [0077]) associated with the memory array, and determine, based on the errors, whether at least one criterion is satisfied (see Ha Fig 11 Ref S114).
As to claim 6, Ha disclose the system of claim 1, wherein
the at least one offset is determined by at least one of adding or subtracting a respective first value to or from a bitline number for each first memory cell (The language "at least one of” implies that only one of the “adding or subtracting” limitations needs to be met.), or adding or subtracting a respective second value to a wordline number for each first memory cell (see Ha Fig 11 Ref S119).
As to claim 7, Ha disclose the system of claim 6, wherein
each of the respective first and second values has a value of 1 or 2 (see Ha Fig 15 Ref S216).
As to claim 11, Ha discloses the system of claim 4, wherein
the criterion is a threshold (see Ha Fig 11 Ref S114), and the threshold is a function of temperature (see Ha Para [0176]).
As to claim 12, Ha discloses the system of claim 1, wherein
the errors are zero-to-one failures (see Ha Fig 9 Refs S4 and RR).
As to claim 14, Ha discloses the system of claim 1, wherein
the first memory cell and the second memory cell are each programmable by the controller to be in an amorphous state or a crystalline state (see Ha Para [0075]).
As to claim 20, Ha discloses a method comprising:
reading first memory cells; determining a read status for the first memory cells (see Ha Fig 11 Ref S113); based on the read status, refreshing the first memory cells (see Ha Fig 11 Ref S116); determining respective physical addresses of second memory cells (see Ha Fig 8 Refs most right MC and WL6) based on physical addresses of the first memory cells (see Ha Fig 8 Refs most right MC and WL5); determining errors associated with the first memory cells (see Ha Fig 11 Ref S114); and in response to determining that the errors exceed at least one threshold, applying a write refresh to the second memory cells (see Ha Fig 11 Refs S116 and S119).
As to claim 21, Ha discloses the method of claim 20, further comprising
adjusting the threshold based on a temperature associated with the memory array (see Ha Fig 11 Ref S114 and Para [0174]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ha, US 20200066342 A1, in view of Bradshaw, US 20190325956 A1.
As to claim 5, Ha discloses the system of claim 1, wherein
the at least one offset comprises a wordline offset.
Ha does not appear to explicitly disclose a bitline offset.
Bradshaw discloses a bitline offset (see Bradshaw Para [0064] and Fig 3 Refs 200B and 200D).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Ha, may implement individual memory cell access for data correction, as disclosed by Bradshaw. The inventions are well known variants of resistive memory technologies, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Bradshaw’s attempt to maintain data (see Bradshaw Para [0070]).
As to claim 13, Ha and Bradshaw disclose system of claim 1, wherein
the memory array is a cross-point memory array (see Bradshaw Para [0021]).
Claim(s) 9 and 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ha, US 20200066342 A1, in view of Yang, US 20170116075 A1.
As to claim 9, Ha discloses the system of claim 4, wherein
the controller is further configured to: adjust the at least one criterion based on temperature (see Ha Para [0176]).
Ha does not appear to explicitly disclose determine a temperature; and adjust the at least one criterion based on the determined temperature.
Yang discloses determine a temperature (see Yang Fig 17 Ref 1106); and adjust the at least one criterion based on the determined temperature (see Yang Fig 9).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Ha, may implement sensors for determining local temperature , as disclosed by Yang. The inventions are well known variants of resistive memory technologies, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Yang’s attempt to identify error conditions (see Yang Para [0031]).
As to claim 15, Ha discloses an apparatus (see Ha Fig 1) comprising:
a memory array (see Ha Fig 1 Ref NVM) comprising at least one first memory cell (see Ha Fig 8 Refs most right MC and WL5); and a controller (see Ha Fig 1 Ref 100) configured to:
determine errors (see Ha Fig 11 Ref S114) associated with the first memory cell; determine, at least one criterion (see Ha Fig 11 Ref S114); determine, based on the errors, whether the at least one criterion is satisfied (see Ha Fig 11 Ref S114); and in response to determining that the criterion is satisfied: determine a physical address of at least one second memory cell (see Ha Fig 8 Refs most right MC and WL6); and apply a write refresh to the second memory cell (see Ha Fig 11 Ref 116).
Ha does not appear to explicitly disclose at least one sensor; collect sensor data from the at least one sensor; and determine, based on the sensor data.
Yang discloses at least one sensor (see Ha Fig 17 Ref 1106; Use of a sensor is inherent.); collect sensor data from the at least one sensor (see Ha Fig 17 Ref 1106); and determine, based on the sensor data (see Yang Fig 9).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Ha, may implement temperature sensing methods , as disclosed by Yang. The inventions are well known variants of resistive memory technologies, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Yang’s attempt to identify error conditions (see Yang Para [0031]).
As to claim 16, Ha and Yang disclose the apparatus of claim 15, wherein
the sensor is a temperature sensor (see Yang Fig 17 Ref 1106).
As to claim 17, Ha and Yang disclose the apparatus of claim 15, wherein
the sensor data is temperature data (see Yang Fig 17 Ref 1106), the criterion is a threshold (see Ha Fig 11 Ref S118), and the threshold is reduced by the controller in response to determining, using the temperature data, that a temperature associated with the memory array has increased (see Ha Para [0176]; Latency reduction requires an error margin threshold to be reduced.).
As to claim 18, Ha and Yang disclose the apparatus of claim 15, wherein
a physical address of the second memory cell is determined using at least one offset from the physical address of the first memory cell (see Ha Fig 11 Ref S119).
As to claim 19, Ha and Yang disclose the apparatus of claim 15, wherein
the controller is further configured to read a status of the first memory cells (see Ha Fig 11 Ref S112), and the read status is a read error due to failure to decode data read from the memory array (see Yang Fig 6B), and the first memory cell is refreshed in response to determining the read error (see Yang Fig 6B Ref 786).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ha, US 20200066342 A1 and Yang, US 20170116075 A1, in view of Sakakibara, US 20220293198 A1.
As to claim 10, Ha and Yang disclose the system of claim 9, wherein
the temperature is a temperature of a semiconductor device (see Ha Para [0176]) which the memory array is formed (see Yang Para [0117]; Forming is a normal operation.).
Ha and Yang do not appear to explicitly disclose a temperature of a semiconductor die.
Sakakibara discloses a temperature of a semiconductor die (see Sakakibara Fig 2A Ref 318 and Para [0095]).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a system, as disclosed by Ha and Yang, may implement sensors for determining local temperature, as disclosed by Sakakibara. The inventions are well known variants of resistive memory technologies, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Sakakibara’s attempt to improve reliability (see Sakakibara Para [0024]).
Response to Arguments
Applicant's arguments filed 02/26/2026 have been fully considered but they are not persuasive.
The language detailing the invention argued in the response is not present in the claimed language and the examiner suggested amended the claim with such language for further consideration. The arguments regarding “a read status” is not present in rejected claims 1 and 15. Ha explicitly discloses a check read operation which determines a status.
Allowable Subject Matter
Claim(s) 8 and 22 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to discloses (as recited in claim 8):
the at least one criterion includes a first threshold and a second threshold; the at least one second memory cell is a first set of cells when a number of the errors exceeds the first threshold; the at least one second memory cell is a second set of cells when the number of the errors exceeds the second threshold; the second threshold is greater than the first threshold; and the second set is larger than the first set.
The prior art does not appear to discloses (as recited in claim 22):
the errors are compared to a first threshold and a second threshold; a first number of second memory cells is refreshed in response to determining that the errors exceed the first threshold; and a second number the second memory cells is refreshed in response to determining that the errors exceed the second threshold.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 04/03/2026