Prosecution Insights
Last updated: October 01, 2026
Application No. 18/734,743

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102
Filed
Jun 05, 2024
Priority
Dec 01, 2023 — TW 112146890
Examiner
BERNSTEIN, ALLISON
Art Unit
Tech Center
Assignee
Siliconware Precision Industries Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
744 granted / 916 resolved
+21.2% vs TC avg
Minimal +3% lift
Without
With
+2.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
16 currently pending
Career history
922
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
39.8%
-0.2% vs TC avg
§102
34.5%
-5.5% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 916 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-22 are pending in the application. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (CN 116705784) (hereinafter, “Chen”) (The machine translation provided is relied on for the following citations.). Re: independent claim 1, Chen discloses in figs. 2-17 an electronic package, comprising: a carrier structure (100) having a first electrical contact pad (fig. 2) and a second electrical contact pad (fig. 2); a passive element (200) disposed on the carrier structure and electrically connected to the first electrical contact pad (fig. 3); an interposer structure (300) disposed on the carrier structure and electrically connected to the second electrical contact pad (fig. 11); and an electronic element (500) disposed on and electrically connected to the passive element (200) and the interposer structure (300). Re: claim 2, Chen discloses in figs. 2-17 the electronic package of claim 1, wherein the carrier structure (100) is formed with a recess (101) accommodating the passive element (200). Re: claim 3, Chen discloses in figs. 2-17 the electronic package of claim 1, wherein a plurality of the passive elements (200) are disposed on the carrier structure (100). Re: claim 4, Chen discloses in figs. 2-17 the electronic package of claim 1, wherein the passive element (200) has a first contact (connected to bottom of 202) and a second contact (connected to top of 202) opposing the first contact, wherein the first contact (connected to bottom of 202) is electrically connected to the first electrical contact pad (fig. 2), and the second contact (connected to top of 202) is electrically connected to the electronic element (500). Re: claim 5, Chen discloses in figs. 2-17 the electronic package of claim 1, wherein the passive element (200) is served as a power transmission element (p. 5 ll. 1-8) for the electronic element (500). Re: claim 6, Chen discloses in figs. 2-17 the electronic package of claim 1, wherein the interposer structure (300) comprises a plate body (302) having a plurality of penetrating conductive vias (within 302), wherein the conductive via is electrically connected to the electronic element (500) and the second electrical contact pad (fig. 14). Re: claim 7, Chen discloses in figs. 2-17 the electronic package of claim 6, wherein the interposer structure (300) further comprises a circuit portion (301) bonded to the plate body (302), wherein the conductive via is electrically connected to the second electrical contact pad via the circuit portion (fig. 11-13). Re: claim 8, Chen discloses in figs. 2-17 the electronic package of claim 6, wherein the interposer structure (300) is disposed on the second electrical contact pad via a conductor (fig. 11). Re: claim 9, Chen discloses in figs. 2-17 the electronic package of claim 1, wherein a plurality of the electronic elements (500) are disposed on the interposer structure (300), and the interposer structure (300) electrically bridges at least two of the plurality of electronic elements (fig. 14). Re: claim 10, Chen discloses in figs. 2-17 the electronic package of claim 1, wherein the interposer structure (300) is served as a signal transmission element (through 301, 302) for the electronic element (500). Re: claim 11, Chen discloses in figs. 2-17 the electronic package of claim 1, further comprising an encapsulation layer (203) encapsulating the passive element (200). Re: independent claim 12, Chen discloses in figs. 2-17 a method of manufacturing an electronic package, comprising: providing a carrier structure (100) having a first electrical contact pad (fig. 2) and a second electrical contact pad (fig. 2); disposing a passive element (200) and an interposer structure (300) on the carrier structure (100), wherein the passive element (200) is electrically connected to the first electrical contact pad (fig. 3), and the interposer structure (300) is electrically connected to the second electrical contact pad (fig. 11); and disposing an electronic element (500) on the passive element (200) and the interposer structure (300), wherein the electronic element (500) is electrically connected to the passive element (200) and the interposer structure (300) (fig. 14). Re: claim 13, see claim 2 rejection above. Re: claim 14, see claim 3 rejection above. Re: claim 15, see claim 4 rejection above. Re: claim 16, see claim 5 rejection above. Re: claim 17, see claim 6 rejection above. Re: claim 18, see claim 7 rejection above. Re: claim 19, see claim 8 rejection above. Re: claim 20, see claim 9 rejection above. Re: claim 21, see claim 10 rejection above. Re: claim 22, see claim 11 rejection above. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin et al. US 2025/0125273 teach a multi-chip package including a passive component including vertical-through-via connector and an interposer. Chen et al. US 2025/0132296 teach a semiconductor package including an interposer including a redistribution structure and a passive device. The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 8/14/2026
Read full office action

Prosecution Timeline

Jun 05, 2024
Application Filed
Aug 19, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
84%
With Interview (+2.9%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 916 resolved cases by this examiner. Grant probability derived from career allowance rate.

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