DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-14 are present for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
2. Claims 1-2 & 11-12 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,020,758 (same assignee/inventor).
Although the claims at issue are not identical, they are not patentably distinct from each other because of the following comparisons:
Claim 1 (this application) obviously recite a similar claimed memory device as the claim 1 (of patent ‘758), which they all includes a nonvolatile memory array having plurality of cell blocks and a controller and the claimed “control logic circuit”, and that the controller send a command to the memory device so as to apply a turn-on voltage to the plurality of word lines. The only minor difference is claim 1 (application) does not recite usage of an “address decoder” coupled to the plurality of word lines. However, this limitation is considered as a conventional feature, which is well-known fact to any skilled person in the memory art because any existing memory device of today must need its own “address decoders” as necessary means, for receiving the address signals (WLs) from the memory controller and/or for receiving the specific control voltages to the respective word lines (of memory cells). Thus, claim 1 (of application) obviously recites a same inventive concept as the claim 1 (of patent ‘758).
Claim 2 (application) recites the control logic circuit to apply the turn-on voltage based on a parameter sent form external device, which also obviously read on the recited usage of “parameter” sent to the memory device by at least a command received from the controller of the patent claim 1.
Claims 11-12 (application) recites similar the limitations of “applying the turn-on voltages in response to the sent parameter from the first and second commands”, which are seen with similar language from the claim 1 (patent ‘758).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1-2, 7 & 11-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 10,026,503).
The applied reference has a common assignee (Samsung) with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claims 1-2 & 11-12, Kim (Fig. 1) shows a nonvolatile memory device comprising a cell array (110) having plurality of cell blocks, an address decoder (120) for generating address signals, a voltage generator (140) for generating the turn-on voltages such as Vpass to the selected word lines for reading or programing purposes, and a memory control as claimed “control logic circuit” for sending the parameters with at least the first and second commands to the address decoder for applying the turn on voltages to either selected word lines and/or unselected word lines as inherent practices in this art. For example, Fig. 7 & 12 below show the controller steps for sending first and second commands with the parameters (i.e., such as pulse with, address & page data) to the word lines; and in response the address decoder 120 will in turn apply necessary turn-on voltages to program or read the selected cells as claimed.
Claim 7, Fig. 2 also shows a plurality of cell strings STR, each string has at least a ground selection transistors (GSL), string selection transistors (SSL), etc.
[AltContent: textbox (At least two command/CMDs and parameter/info are sent to the address decoder for a programming operation and for applying the “turn-on” voltages to the WLs. (Fig. 7))][AltContent: textbox (Address decoders apply the “Turn-ON”
voltages = Vpass to plurality of word lines in response to the commands sent from memory controller (Fig. 12))][AltContent: arrow][AltContent: arrow]
PNG
media_image1.png
548
514
media_image1.png
Greyscale
[AltContent: arrow][AltContent: arrow]
PNG
media_image2.png
610
546
media_image2.png
Greyscale
Allowable Subject Matter
4. The following claims 3-6 & 13-14 are objected as being dependent upon their parent/rejected claims above, but they tentatively contain the following novel limitations, which are not clearly suggested by the prior arts cited herein, nor seen elsewhere at this time:
- Claims 3 recites novel usage of different parameter info such as plane, start block address, turn-on voltage level, and pre-charge time, etc.
- Claim 4 recites novel usage of different voltage levels for the turn-on voltage, etc.
- Claim 5 recites novel limitations of different default times such as, i.e., pre-charge time, given time and specific time for input/command period, etc.
- Claim 6 recites novel usage of “plane bit” as parameter for the applying the turn-on voltage.
Claims 13-14 recite novel usage of both idle state and busy state for the first and second time intervals, respectively, etc.
Additionally, the claims 8-10 are also allowable for reciting a novel method steps using the “ready/busy” signal of a busy state during a first time after the second command input period, etc., and wherein the parameter includes information about a plane, information about a start block address, information about the number of memory blocks, information about a turn-on voltage level, and information about a pre-charge time.
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VIET Q NGUYEN/Primary Examiner, Art Unit 2827