DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
1. The specification is objected because of the following reasons:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
In par. [0001]: insert US Patent no. 12041794.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2017/0141032).
Re claim 1, Lee teaches, under BRI, Figs. 1, 2A-B, 5A-B, 6 & 16, [0027, 0028, 0043, 0055, 0061, 0065, 0074, 0078], a semiconductor storage device comprising
-a stacked body (LML, UML, Fig. 5B) in which a plurality of conductive layers (CP) and a plurality of insulating layers (IDL) are alternately stacked one by one in a stacking direction (vertical) , the stacked body (LML, UML) including a memory region (P1) in which a plurality of memory cells (Figs. 2A, B) are disposed and a staircase region (in WLSTS3, Fig. 6) in which end portions of the plurality of conductive layers (CP) form a staircase shape, the memory region (P1) and the staircase region being arranged in a first direction (horizontal) crossing the stacking direction (vertical), wherein
in the stacked body (LML, UML), the staircase region includes a first portion (indicated) ascending in a direction toward the memory region (P1) to reach an uppermost conductive layer (CP) of the conductive layers (CP) and a second portion (indicated) ascending in a direction away from the memory region (P1) to reach the uppermost conductive layer (CP), the first portion and the second portion being arranged in the first direction (horizontal),
in the first portion, sub-stairs (indicated, Fig. 6) and a first difference in level (indicated) are disposed in order in the direction toward the memory region (P1), each stair of the sub-stairs including only one layer of the conductive layers (CP), and the first difference in level (indicated) being larger than a respective difference in level of each stair of the sub-stairs (indicated), and in the second portion, lower stairs (indicated, Fig. 6) of which stair each includes only one layer of the conductive layers (CP) and upper stairs (indicated, Fig. 6) of which stair each includes only one layer of the conductive layers (CP) are disposed in order in the direction away from the memory region (P1), and a second difference in level (indicated) larger than a respective difference in level of each stair of the lower and upper stairs (indicated) is disposed between the lower stairs and the upper stairs (indicated) in the first direction (horizontal).
Note: Figs. 5B & 16 show similar stacked body & stair regions as in Fig. 6.
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Re claim 2, Lee teaches, Fig. 6, wherein in the sub-stairs (indicated) and the lower and upper stairs (indicated), each stair has a terrace portion that does not overlap in the stacking direction (vertical) with an upper conductive layer (CP) of a conductive layer (CP) included in the stair itself among the conductive layers (CP).
Re claim 3, Lee teaches, Fig. 6, wherein the first difference in level (indicated) and the second difference in level (indicated) extend in a direction crossing a surface formed by the terrace portion and any terrace portions are not disposed in the first difference in level and the second difference in level (indicated).
Re claim 4, Lee teaches, Fig. 6, wherein the lower stairs (indicated) are provided symmetrically (at center point between indicated lower stairs & sub-stairs) to a lower part of the sub-stairs (indicated) in the first direction (horizontal).
Re claim 5, Lee teaches, Fig. 6, wherein a number of conductive layers (CP) in the lower part of the sub-stairs (indicated) and a number of conductive layers (CP) in the lower stairs (indicated) are equal to each other, and a number of conductive layers (CP) in a residual upper part of the sub-stairs (indicated) and a number of conductive layers (CP) in the upper stairs (indicated) are equal to each other.
Re claim 6, Lee teaches, Fig. 6, wherein the residual upper part of the sub-stairs (indicated) and a lower portion of the second difference in level (indicated) face each other (across IB1) in the first direction (horizontal).
Re claim 7, Lee teaches, indicated in Fig. 6, wherein a magnitude (e.g., size) of the first difference in level (indicated) is substantially equal to a magnitude of the second difference in level (indicated) (based on number selected layers).
Re claim 8, Lee teaches, Figs. 6-7A, [0071], wherein in the sub-stairs (indicated), a contact (CTP) connected to a conductive layer (CP) included in the sub-stairs among the conductive layers (CP) is disposed.
Re claim 9, Lee teaches, Figs. 2A, B & 6, wherein the conductive layer (CP) included in the sub-stairs (indicated) is coupled to a memory cell among the memory cells (Fig. 2A, B).
Re claim 10, Lee teaches, Figs. 2A, B & 6, wherein a portion of a conductive layer (CP) included in the lower stairs (indicated) and a portion of a conductive layer (CP) included in the upper stairs (indicated) (in 2nd portion) among the conductive layers (CP) are not coupled to any memory cell among the memory cells (Figs. 2A, B, spacing by IB1).
Re claim 11, Lee teaches, under BRI, Figs. 1, 2A, 2B, 6 & 16, [0027, 0028, 0043, 0055, 0061, 0065, 0074], a semiconductor storage device comprising
-a stacked body (LML, ULM, Fig. 5B) in which a plurality of conductive layers (CP) and a plurality of insulating layers (ILD) are alternately stacked one by one in a stacking direction (vertical), the stacked body (LML, ULM) including a memory region (P1) in which a plurality of memory cells (Figs. 2A, 2B) are disposed and a staircase region (in WLSTS3, Fig. 6) in which end portions of the plurality of conductive layers (CP) form a staircase shape, the memory region (P1) and the staircase region being arranged in a first direction (horizontal) crossing the stacking direction (vertical), wherein
in the stacked body (LML, ULM), the staircase region (in WLSTS3) includes a first portion (indicated, Fig. 6) ascending in a direction toward the memory region (P1) and a second portion (indicated, Fig. 6) ascending in a direction away from the memory region (P1), the first portion and the second portion being arranged in the first direction,
in the first portion, sub-stairs (indicated, Fig. 6) and a first difference in level (indicated) are disposed in order in the direction toward the memory region (P1), each stair of the sub-stairs including only one layer of the conductive layers (CP), and the first difference in level (indicated) being larger than a respective difference in level of each stair of the sub-stairs (indicated),
in the second portion, lower stairs (indicated, Fig. 6) of which stair each includes only one layer of the conductive layers (CP) and upper stairs (indicated) of which stair each includes only one layer of the conductive layers (CP) are disposed in order in the direction away from the memory region (P1), and a second difference in level (indicated) larger than a respective difference in level of each stair of the lower and upper stairs (indicated, Fig. 6) is disposed between the lower stairs and the upper stairs (indicated) in the first direction (horizontal), and
a lower end of the sub-stairs (indicated) and a lower end of the lower stairs (indicated) are substantially in same level in the stacking direction (vertical), and an upper end of the first difference in level (indicated) and an upper end of the upper stairs (indicated) are substantially in same level (as horizontal line) in the stacking direction (vertical) (based on selected numbers of layers).
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Re claim 12, Lee teaches, Fig. 6, in the sub-stairs (indicated) and the lower and upper stairs (indicated), each stair has a terrace portion that does not overlap in the stacking direction (vertical) with an upper conductive layer (higher CP) of a conductive layer included in the stair itself among the conductive layers (CP).
Re claim 13, Lee teaches, Fig, 6, wherein the first difference in level and the second difference in level (indicated, vertical levels adjacent to indicated stairs) extend in a direction crossing a surface formed by the terrace portion and any terrace portions are not disposed in the first difference in level and the second difference in level (indicated).
Re claim 14, Lee teaches, Fig.6, wherein the lower stairs (indicated) are provided symmetrically (at center point of IB1) to a lower part of the sub-stairs (indicated) in the first direction (horizontal).
Re claim 15, Lee teaches, Fig. 6, wherein a number of conductive layers (consider bottom two layers CP) in the lower part of the sub-stairs (indicated) and a number of conductive layers (bottom two layers CP) in the lower stairs (indicated) are equal to each other, and a number of conductive layers (consider upper two CP layers) in a residual upper part of the sub-stairs (indicated) and a number of conductive layers (consider two CP layers) in the upper stairs (indicated) are equal to each other.
Re claim 16, Lee teaches, Fig. 6, wherein the residual upper part (upper two CP layers) of the sub-stairs (indicated) and a lower portion of the second difference in level (indicated) face each other in the first direction (horizontal).
Re claim 17, Lee teaches, Fig. 6, wherein a magnitude (e.g., size) of the first difference in level (indicated) is substantially equal to a magnitude of the second difference in level (indicated) (e.g., based on numbers of selected layers).
Re claim 18, Lee teaches, Figs. 6-7A, [0067], wherein in the sub-stairs (indicated), a contact (CTP) connected to a conductive layer (CP) included in the sub-stairs among the conductive layers (CP) is disposed.
Re claim 19, Lee teaches, Figs. 2A, B & 6, wherein the conductive layer (CP) included in the sub-stairs (indicated) is coupled to a memory cell among the memory cells (Fig. 2A, B).
Re claim 20, Lee teaches, Figs. 2A, B & 6, wherein a portion of a conductive layer (CP) included in the lower stairs (indicated) and a portion of a conductive layer (CP) included in the upper stairs (indicated) (in 2nd portion) among the conductive layers (CP) are not coupled to any memory cell among the memory cells (Figs. 2A, B, spacing by IB1).
Conclusion
3. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamamoto (US 2019/0273089, Figs. 3 & 12) discloses semiconductor device including stacked body with conductive layers and insulating layers and staircase portion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 8/13/26
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