DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Oath/Declaration
2. The oath/declaration filed on 06/05/2024 is acceptable.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
4. The specification is objected to for the following reason: The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed (see MPEP 606.01).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-5 and 12-15 are rejected under 35 U.S.C. 103(a) as being unpatentable over KURASHIMA N (JP-2012015192-A1) in view of 김현기 (KR-102127772-B1).
Regarding claim 1, KURASHIMA N discloses a package structure, comprising a first substrate (12), a second substrate (20), a first chip (14), a second chip (34), a heat sink (24) and an inter-board connection structure (18), wherein
the second substrate (20) is provided with a first opening penetrating through an upper surface and a lower surface of the second substrate (20);
the first chip (14) is mounted to an upper surface of the first substrate (12), and the first chip (14) is electrically connected to the first substrate (12);
the second substrate (20) is mounted to the upper surface of the first substrate (12), the inter-board connection structure (18) is positioned between the lower surface of the second substrate (20) and the upper surface of the first substrate (12), the second substrate (20) is electrically connected to the first substrate (12) through the inter-board connection structure (18), and the first opening in the second substrate (20) at least exposes a part of the back side of the first chip (14);
the second chip (34) is mounted to the upper surface of the second substrate (20), and the second chip (34) is electrically connected to the second substrate (20); and
the heat sink passes through the first opening (Figs. 5a-5b and 8 and English Text).
KURASHIMA N discloses the features of the claimed invention as discussed above, but does not disclose the heat sink is mounted to the back side of the first chip through the first opening.
김현기, however, discloses the heat sink (11) is mounted to the back side (27) of the first chip (25) through the first opening (by a first thermal interface material layer (TIM layer) 8) Fig. 16 and English Text).
It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of KURASHIMA N to provide the heat sink is mounted to the back side of the first chip through the first opening as taught by 김현기 for a purpose of providing the heat dissipating efficiency of the first chip.
Regarding claim 2, KARASHIMA N and 김현기 (citations to
KARASHIMA N unless otherwise noted) discloses wherein the first chip (14) has a size larger than that of the first opening, and the first chip (14) has a thickness thinner than that of the inter-board connection structure (18) (Fig. 16 and English Text).
Regarding claim 3, KARASHIMA N and 김현기 (citations to
KARASHIMA N unless otherwise noted) discloses wherein the surface of the back side of the first chip (14) outside the first opening is adhered to the lower surface of the second substrate (31/41) at an edge of the first opening through sealing material (81), and the first opening exposes the back side of the first chip (14) between the sealing material (81) (Fig. 8 in KARASHIMA N and Fig. 16 in 김현기).
Regarding claim 4, KARASHIMA N and 김현기 (citations to
KARASHIMA N unless otherwise noted) discloses wherein the sealing material (81) completely seals, partially seals, or does not seal the space between the second substrate (31/41) at the edge of the first opening and the surface of the back side of the first chip (25) outside the first opening (Fig. 16 in 김현기).
Regarding claim 5, KARASHIMA N and 김현기 (citations to KARASHIMA N unless otherwise noted) discloses wherein a molding compound (22) is filled between the first substrate (12) and the second substrate (20) (Fig. 6).
With respect to process claim 12 prior art device renders obvious a claimed process, in its normal and usual operation, and it would necessarily perform the method claim. MPEP2112.02.
Regarding claim 13, KARASHIMA N and 김현기 (citations to KARASHIMA N unless
otherwise noted) discloses wherein the first chip (14) has a size larger than that of the first opening, and the first chip (14) has a thickness thinner than that of the inter-board connection structure (18) (Fig. 8).
Regarding claim 14, KARASHIMA N and 김현기 (citations to
KARASHIMA N unless otherwise noted) discloses wherein the surface of the back side of the first chip (25) outside the first opening is adhered to the lower surface of the second substrate (31/41) at an edge of the first opening through sealing material (81), and the first opening exposes the back side of the first chip between the sealing material (81) (Fig. 16 in 김현기).
Regarding claim 15, KARASHIMA N and 김현기 (citations to
KARASHIMA N unless otherwise noted) discloses wherein the sealing material (81) completely seals, partially seals, or does not seal a space between the second substrate (31/41) at the edge of the first opening and the surface of the back side of the first chip (25) outside the first opening (Fig. 16 in 김현기).
Allowable Subject Matter
6. The following is a statement of reason for the indication of allowable subject matter:
Claims 6-11 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Arts
7. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
PARK M (KR-20130035805-A) discloses a package structure, comprising a lower package (10) includes a first substrate (110) having a first semiconductor chip. An upper package (20) includes a second substrate (210) having a second semiconductor chip. A heat sink (250) is formed between the upper and the lower package. A connection terminal (120) electrically connects the lower package to the upper package. A first heat spreader (170) is arranged on the first semiconductor chip (Fig. 1 and English Text).
Conclusion
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHUC T DANG/Primary Examiner, Art Unit 2897
