DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. There does not seem to be antecedent for “the summation.”
Claim(s) 4 depends from claim 3, and as such is also rejected for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 5-6 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20250078881 to Huang et al. (“Huang”).
As to claim 1, Huang teaches A memory cell array structure (As found in at least FIG. 3B), comprising: a plurality of memory cells organized into a plurality of rows and columns (As found in at least FIG. 3B); a plurality of input lines, wherein each input line is connected to memory cells in a selected row, and wherein the plurality of input lines form a plurality of input line groups (As found in at least FIG. 3B: plurality of input lines H1-Hi connect to memory cells in the array in a selected row, H1-Hi form an input line group); a plurality of output lines, wherein each output line is connected to memory cells in a selected column, and wherein the plurality of output lines form a plurality of output line groups (As found in at least FIG. 3B: plurality of output lines L1-Lj connect to memory cells in the array in a selected Column, L1-Lj form an output line group); a multiplexer having multiplexer inputs and multiplexer outputs (As found in at least FIG. 3B: Multiplexer having inputs connected to array and outputs connected to 300), wherein the multiplexer inputs are connected to the output line groups (As found in at least FIG. 3B: inputs of Multiplexer connected to output line group L1-Lj); neuron circuits connected to the multiplexer outputs (As found in at least FIG. 3B: neuron circuit 300 connected to Multiplexer output); and wherein the memory cell array simulates a neural network in which the plurality of input lines simulate input layer neurons of the neural network, and the plurality of output lines simulate output layer neurons of the neural network (As found in at least FIGS. 3A-3B, [0020-0021]: the array in FIG. 3B simulates a neural network as presented in at least FIG. 3A).
As to claim 5, Huang teaches selector that sequentially selects the input data groups to limit the selected number of cells in each output line in the selected output line group (As found in at least FIGS. 3A-3B, 5 and [0114]: inputs are sequential, pulsed, and thus limits cells in the output lines).
As to claim 6, Huang teaches wherein the multiplexer sequentially selects the output line groups and passes the summation of the cell currents to the neuron circuits (As found in at least FIGS. 3A-3B: Multiplexer selects output lines from array, and passes the resulting information to the neuron 300).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7 is/are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by US 20210232905 to Dalgaty et al. (“Dalgaty”).
As to claim 7, Dalgaty teaches a 3D cell structure (a 3D structure of memory cells; paragraph [0O75]), comprising: a plurality of blocks, wherein each block comprises an input buffer, an array, and a neuron circuit (the network is formed by blocks comprising an input buffer, an array, and a neuron circuit: paragraphs [0068], [0113]), and wherein each neuron circuit outputs an output data group (neuron circuits output data to the output line groups; paragraph [0070]); a plurality of data buffers having buffer inputs and buffer outputs, wherein the plurality of buffers inputs are configured to receive the output data groups from the plurality of neuron circuits, respectively (buffer 1402 receives input signals and release output signals, where the input signals are from the neuron circuits 1404; paragraph [0113]); a plurality of activation circuits having circuit inputs and circuit outputs, wherein the plurality of circuit inputs are connected to the plurality of buffer outputs, respectively (memory cell 902 stores activation circuits with input line 904 and output line connected to the current buffer 1402; paragraphs [0099], [0113]), and wherein the plurality of circuit outputs are configured to output activation results (activation circuits configured to output activation results; paragraph [0099]); and wherein the 3D cell structure simulates a neural network in which the plurality of input buffers simulate input neurons groups of the neural network (the array simulates a neural network, where the input buffers simulate input neuron groups; paragraphs [0017], [0113]), the plurality of data buffers simulate output neuron groups of the neural network (buffer outputs may simulate output neuron groups; paragraph [0123]), and the plurality of activation circuits simulate activation functions of the neural network (the activation circuit in the memory cell asserts a signal corresponding to its column line to cause current conduction; paragraph [0099]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250078881 to Huang et al. (“Huang”) in view of U.S. Patent/Publication No. 20240419955 to Vrudhula et al. (“Vrudhula”).
As to claim 2, while Huang teaches substantially the claimed invention, the teachings may not expressly include: wherein the plurality of memory cells comprise one of floating body cells, flash memory cells, resistive random-access memory cells, ferroelectric random-access memory cells, magneto-resistive random-access memory cells, phase-change memory cells, and mem-transistor cells.
Yet, Vrudhula in relevant and complementary teachings teaches wherein the plurality of memory cells comprise one of floating body cells, flash memory cells, resistive random-access memory cells, ferroelectric random-access memory cells, magneto-resistive random-access memory cells, phase-change memory cells, and mem-transistor cells (As found in at least [0054]: memory technology used, at least, resistive random-access memory).
Huang and Vrudhula are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having an array of cells that can be anyone of floating body cells, flash memory cells, resistive random-access memory cells, ferroelectric random-access memory cells, magneto-resistive random-access memory cells, phase-change memory cells, and mem-transistor cells.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Huang as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Vrudhula also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: memory devices come in very different technologies; the teachings of Vrudhula make this evident. Different memory technologies may be suitable for different application.
Therefore, it would have been obvious to combine Huang with Vrudhula to make the above modification.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250078881 to Huang et al. (“Huang”) in view of U.S. Patent/Publication No. 20230138695 to Kumar et al. (“Kumar”).
As to claim 3, at least Kumar teaches where the neuron circuits comprise at least one of an analog-to-digital converter, operational amplifier, or a comparator to convert the summation of cell currents into digital data (As found in at least FIG. 5 and [0064]).
Huang and Kumar are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: systems having neural networks that may include neurons and memory arrays.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Huang as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Kumar also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: as set forth in at least [0064], Kumar proposes conversion of analog signals to digital signal; this is done routinely to ease data manipulation in the digital realm.
Therefore, it would have been obvious to combine Huang with Kumar to make the above modification.
As to claim 4, Kumar teaches where the analog-to-digital converter, operational amplifier, or comparator circuits also perform an activation function (As found in at least [0064], at least the analog-to-digital performs an “activation function:” it activates a function of conversion analog information into digital information).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827