Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 09/14/2026 have been fully considered but they are not persuasive.
The Applicant argues that in regard to claim 1 that the Shin prior art, does not teach the limitation of “wherein the first pixel row and the second pixel row are consecutive pixel rows.”
In response to this argument, the Examiner directs the applicant’s attention to Shin prior art, which clearly teaches the limitation of a second-first pixel circuit portion (RSP in region PX11) positioned in a second pixel row and the first pixel column, wherein the first pixel row and the second pixel row are consecutive pixel rows (note: the row and column of the pixels determined based on the viewer location. For example, if the row is rotated by 180 degree, it will become a column) (see Shin, Figs.1 and 3 as shown below).
In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004).
The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the Shin prior art reference does meet all the limitation in claim 1.
Allowable Subject Matter
Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “a first-zeroth dummy pixel circuit portion disposed in a dummy pixel column adjacent to the first pixel row and the first pixel column and spaced apart from the second pixel column;
a second-zeroth dummy pixel circuit portion disposed in the second pixel row and the dummy pixel column;
a dummy data line overlapping the first-zeroth dummy pixel circuit portion and the second-zeroth dummy pixel circuit portion in the plan view, electrically connected to the second-zeroth dummy pixel circuit portion, and extending in the column direction; and
a second-zeroth light emitting portion electrically connected to the second-zeroth dummy pixel circuit portion”, as recited in claim 9.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “a second-zeroth light emitting portion electrically connected to the first-third pixel circuit portion through the first-third light emitting portion; and
a connection electrode electrically connecting an anode electrode of the first-third light emitting portion and an anode electrode of the second-zeroth light emitting portion”, as recited in claim 11.
Claims 13-24 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 13, Park et al. (U.S. 2023/0051074 A1, hereinafter refer to Park) teaches a display device (see Wang, Fig.12 as shown below and ¶ [0119]- ¶ [0121], ¶ [0147], ¶ [0154], ¶ [0173], and ¶ [0176]) comprising:
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a plurality of first pixel circuit (PXC4) portions disposed in a row direction along a first pixel row (see Wang, Fig.12 as shown above and ¶ [0119]- ¶ [0121], ¶ [0147], ¶ [0154], ¶ [0173], and ¶ [0176]);
a plurality of second pixel circuit portions (PXC2) disposed in the row direction along a second pixel row (see Wang, Fig.12 as shown above and ¶ [0119]- ¶ [0121], ¶ [0147], ¶ [0154], ¶ [0173], and ¶ [0176]);
a plurality of extension lines (PCE4) including a plurality of first extension lines (PCE4) electrically connected one-to-one with the plurality of first pixel circuit portions (PXC4) and a plurality of second extension lines (PCE2) electrically connected one-to-one with the plurality of second pixel circuit portions (PXC2) (see Wang, Fig.12 as shown above and ¶ [0119]- ¶ [0121], ¶ [0147], ¶ [0154], ¶ [0173], and ¶ [0176]);
a plurality of first light emitting portions (LE4) electrically connected one-to-one with the plurality of first extension lines (PCE4) (see Wang, Fig.12 as shown above and ¶ [0119]- ¶ [0121], ¶ [0147], ¶ [0154], ¶ [0173], and ¶ [0176]); and
a plurality of second light emitting portions (LE2) electrically connected one-to-one with the plurality of second extension lines (PCE2) (see Wang, Fig.12 as shown above and ¶ [0119]- ¶ [0121], ¶ [0147], ¶ [0154], ¶ [0173], and ¶ [0176]).
Wang is silent upon explicitly disclosing wherein a plurality of sub-data lines electrically connected to the plurality of first pixel circuit portions and the plurality of second pixel circuit portions, and extending in a column direction crossing the row direction.
For support see Shiomi (U.S. 2016/0163270 A1, hereinafter refer to Shiomi) teaches wherein a plurality of sub-data lines (SL) electrically connected to the plurality of first pixel circuit portions (Gp) and the plurality of second pixel circuit portions (Gp), and extending in a column direction crossing the row direction (see Shiomi, Fig.5).
The prior arts of record do not anticipate and do not render obvious such limitations of Claim 13 as: " wherein the number of the plurality of extension lines overlapping in a plan view a sub-data line disposed in a Nth pixel column among the plurality of sub-data lines is a same as the number of the plurality of extension lines overlapping in the plan view to on a sub-data line disposed in a (N+2)th pixel column among the plurality of sub-data lines (where N=4M+1 and M is an integer equal to or greater than 0).”
Claims 14-24 are allowed for the same reasons as claim 13, from which they depend.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shin et al. (U.S. 2024/0215351 A1, hereinafter refer to Shin).
Regarding Claim 1: Shin discloses a display device (see Shin, Figs.1-3 as shown below and ¶ [0002]) comprising:
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a first-first pixel circuit portion (BSP in region PX11) positioned in a first pixel row and a first pixel column (see Shin, Fig.3 as shown above);
a first-second pixel circuit portion (RSP in region PX12) positioned in the first pixel row and a second pixel column (see Shin, Fig.3 as shown above);
a second-first pixel circuit portion (RSP in region PX11) positioned in a second pixel row and the first pixel column, wherein the first pixel row and the second pixel row are consecutive pixel rows (note: the row and column of the pixels determined based on the viewer location. For example, if the row is rotated by 180 degree, it will become a column) (see Shin, Figs.1 and 3 as shown above);
a second-second pixel circuit portion (BSP in region PX12) positioned in the second pixel row and the second pixel column (see Shin, Fig.3 as shown above);
a first sub-data line (DL1) overlapping the first-first pixel circuit portion (BSP in region PX11) and the second-first pixel circuit portion (RSP in region PX11) in a plan view and extending in a column direction (see Shin, Fig.3 as shown above); and
a second sub-data line (DL2) overlapping the first-second pixel circuit portion (RSP in region PX12) and the second-second pixel circuit portion (BSP in region PX12) in the plan view ad extending in the column direction (see Shin, Fig.3 as shown above),
wherein each of the first-first pixel circuit portion (BSP in region PX11) and the second-second pixel circuit portion (BSP in region PX12) is electrically connected to the first sub-data line (DL1) (see Shin, Fig.3 as shown above), and
each of the first-second pixel circuit portion (RSP in region PX11) and the second-first pixel circuit (RSP in region PX12) portion is electrically connected to the second sub-data line (DL2) (see Shin, Fig.3 as shown above).
Regarding Claim 2: Shin discloses a display device as set forth in claim 1 as above. Shin further teaches wherein the first-first pixel circuit portion (BSP in region PX11) and the first-second pixel circuit portion (RSP in region PX11) are symmetrical to each other (see Shin, Fig.3 as shown above), and
the second-first pixel circuit portion (RSP in region PX12) and the second-second pixel circuit portion (BSP in region PX12) are asymmetrical to each other (see Shin, Fig.3 as shown above).
Regarding Claim 3: Shin discloses a display device as set forth in claim 1 as above. Shin further teaches wherein the first-first pixel circuit portion (BSP in region PX11) includes a first-first semiconductor pattern (see Shin, Fig.3 as shown above),
the first-second pixel circuit portion (RSP in region PX11) includes a first-second semiconductor pattern (see Shin, Fig.3 as shown above),
the second-first pixel circuit portion (RSP in region PX12) includes a second-first semiconductor pattern (see Shin, Fig.3 as shown above),
the second-second pixel circuit portion (BSP in region PX12) includes a second-second semiconductor pattern (see Shin, Fig.3 as shown above),
the first-first semiconductor pattern and the first-second semiconductor pattern are symmetrical to each other (see Shin, Fig.3 as shown above), and
the second-first semiconductor pattern and the second-second semiconductor pattern are asymmetrical to each other (see Shin, Fig.3 as shown above).
Regarding Claim 4: Shin discloses a display device as set forth in claim 3 as above. Shin further teaches wherein each of the first-first semiconductor pattern and the second-second semiconductor pattern is electrically connected to the first sub-data line (DL1) (see Shin, Fig.3 as shown above), and
each of the first-second semiconductor pattern and the second-first semiconductor pattern is electrically connected to the second sub-data line (DL2) (see Shin, Fig.3 as shown above).
Regarding Claim 5: Shin discloses a display device as set forth in claim 1 as above. Shin further teaches wherein a first-third pixel circuit portion (BSP in region PX13) positioned in the first pixel row and a third pixel column (note: PX13 and PX14 of Fig.1 to have identical configuration as PX11 and PX12 of Fig.1, which is demonstrated in Fig.13) (see Shin, Figs.1 and 3 as shown above);
a first-fourth pixel circuit portion (RSP in region PX14) positioned in the first pixel row and a fourth pixel column (note: PX13 and PX14 of Fig.1 to have identical configuration as PX11 and PX12 of Fig.1, which is demonstrated in Fig.13) (see Shin, Figs.1 and 3 as shown above);
a second-third pixel circuit portion (RSP in region PX13) positioned in the second pixel row and the third pixel column (note: PX13 and PX14 of Fig.1 to have identical configuration as PX11 and PX12 of Fig.1, which is demonstrated in Fig.13) (see Shin, Figs.1 and 3 as shown above);
a second-fourth pixel circuit portion (BSP in region PX 14) positioned in the second pixel row and the fourth pixel column (note: PX13 and PX14 of Fig.1 to have identical configuration as PX11 and PX12 of Fig.1, which is demonstrated in Fig.13) (see Shin, Figs.1 and 3 as shown above);
a third sub-data line (DL1) overlapping the first-third pixel circuit portion (BSP in region PX13) and the second-third pixel circuit portion (RSP in region PX14) in the plan view and extending in the column direction (see Shin, Figs.1 and 3 as shown above); and
a fourth sub-data line (DL2) overlapping the first-fourth pixel circuit portion (RSP in region PX 14) and the second-fourth pixel circuit portion (BSP in region PX14) in the plan view ad extending in the column direction (see Shin, Figs.1 and 3 as shown above),
wherein each of the first-third pixel circuit portion (BSP in region PX13) and the second-fourth pixel circuit portion (BSP in region PX14)is electrically connected to the third sub-data line (DL1) (see Shin, Figs.1 and 3 as shown above), and
each of the first-fourth pixel circuit portion (RSP in region PX14) and the second-third pixel circuit portion (RSP in region PX14) is electrically connected to the fourth sub-data line (DL2) (BSP in region) (see Shin, Figs.1 and 3 as shown above).
Regarding Claim 6: Shin discloses a display device as set forth in claim 5 as above. Shin further teaches wherein a first-first light emitting portion (150) electrically connected to the first-first pixel circuit portion (BSP in region PX11) and that emits light of a first color (see Shin, Figs.1-3 as shown above);
a first-second light emitting portion (150) electrically connected to the first-second pixel circuit portion (RSP in region PX12) and that emits light of a second color (see Shin, Figs.1-3 as shown above);
a first-third light emitting portion (150) electrically connected to the first-third pixel circuit portion (BSP in region PX13) and that emits light of a third color (see Shin, Figs.1-3 as shown above); and
a first-fourth light emitting portion (150) electrically connected to the first-fourth pixel circuit portion (RSP in region PX14) and that emits light of the second color (see Shin, Figs.1-3 as shown above).
Regarding Claim 7: Shin discloses a display device as set forth in claim 6 as above. Shin further teaches wherein a second-first light emitting portion (150) electrically connected to the second-first pixel circuit portion (RSP in region PX11) and that emits light of the second color (see Shin, Figs.1-3 as shown above);
a second-second light emitting portion (150) electrically connected to the second-second pixel circuit portion (BSP in region PX12) and that emits light of the first color (see Shin, Figs.1-3 as shown above);
a second-third light emitting portion (150) electrically connected to the second-third pixel circuit portion (RSP in region PX13) and that emits light of the second color (see Shin, Figs.1-3 as shown above); and
a second-fourth light emitting portion (150) electrically connected to the second-fourth pixel circuit portion (BSP in region PX 14) and that emits light of the third color (see Shin, Figs.1-3 as shown above).
Regarding Claim 8: Shin discloses a display device as set forth in claim 7 as above. Shin further teaches wherein the first-first light emitting portion (150) and the first-third light emitting portion (150) are arranged in a row direction crossing the column direction (see Shin, Figs.1-3 as shown above),
the first-second light emitting portion (150) and the first-fourth light emitting portion (150) are arranged in the row direction and are spaced apart from the first-first light emitting portion (150) and the first-third light emitting portion (150) in the column direction (see Shin, Figs.1-3 as shown above),
the second-second light emitting portion (150) and the second-fourth light emitting portion (150) are arranged in the row direction and are spaced apart from the first-second light emitting portion (150) and the first-fourth light emitting portion (150) in the column direction (see Shin, Figs.1-3 as shown above), and
the second-first light emitting portion (150) and the second-third light emitting portion (150) are arranged in the row direction and are spaced apart from the second-second light emitting portion (150) and the second-fourth light emitting portion (150) in the column direction (see Shin, Figs.1-3 as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
