DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined 33under the first inventor to file provisions of the AIA .
Claim status
Claims 1-19 are pending; claims 1, 18 and 19 are independent.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 11-15 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2023/0050569), and further in view of Fujii (US 2014/0333676).
Regarding claims 1, 18 and 19, Dong teaches a display device (fig. 1, a display device 10), a display panel (a display panel 1), and a method for driving a display panel (fig. 6),
wherein the display panel (figs 2, 4, a display panel 1) comprises a demultiplexer fig. 2, 4 and a time-division multiplexing circuit 106), a data terminal (figs 2, 4, data signal terminal 107), data lines (figs 2, 4, data lines 103 and 104), and sub-pixels (fig. 2, 4 and pixels and Para 0045)), the demultiplexer comprises an input terminal connected to the data terminal and output terminals connected to n data lines of the data lines respectively, n is an integer and n≥2 (figs 2, 4 and Para 0046), the demultiplexer further comprises n switches, each switch is connected between the input terminal and one of the output terminals and connected to a corresponding one data line of the n data lines (fig. 4, the gating devices 114 and Para 0062), the data lines extend in a first direction and are connected to the sub-pixels (fig. 4, the data lines 103 and 104), and
the sub-pixels comprise a first sub-pixel, a second sub-pixel, and a third sub-pixel ((figs 2, 4 and Para 0045, wherein the sub-pixel array 101 includes a plurality of sub-pixels (as indicated by Pixel in FIG. 2) arranged in a plurality of rows and a plurality of columns),
wherein the method comprises:
supplying, by the data terminal, data signals to the input terminal of the demultiplexer, and turning on the switches for predetermined time durations respectively to input the data signals to the n data lines (fig 4 and Para 0062, wherein control terminals of the two gating devices 114 are coupled to the gating signal control circuit, so as to receive the gating signal MUX1. A first terminal of a first gating device 114 is coupled to a first data line 103 of a first column (i.e., the first data line 103 coupled to all sub-pixels located in the odd-numbered rows in sub-pixels located in the first column), and a second terminal of the first gating device 114 is coupled to a data signal sub-terminal Data1 in the data signal terminal 107, the connection manners of gating devices in other gating branches are the same),
wherein the data signals comprise a first data signal corresponding to the first sub-pixel, a second data signal corresponding to the second sub-pixel, and a third data signal corresponding to the third sub-pixel (fig. 4 and Para 0069, wherein the data signal terminal 107 includes two data signal sub-terminals, i.e., Data1 and Data2, the data signal sub-terminal Data1 and the data signal sub-terminal Data2 are coupled to a first and a second data lines 103 via the first gating branch 110 and the second gating branch 111, respectively. The data signal sub-terminal Data1 and the data signal sub-terminal Data2 also are coupled to a first and a second data lines 104 via the third gating branch 112 and the fourth gating branch 113, respectively. This arrangement allows different data signals to be written into data lines connected to each gating branch in the same time period); and .
wherein a turned-on time duration of the switch, which corresponds to a time period in which the first data signal is supplied to the input terminal of the demultiplexer, is the longest (fig. 8, Paras 0105-0108 and 0115-0116, wherein d represents acting durations of the data signals input to the first gating branch 110 and the third gating branch 112 and e represents acting durations of the data signals input to the second gating branch 111 and the fourth gating branch 113, from the drawing e is greater than d, so the time duration of the switches coupled to the even numbered column sub-pixels is longer than the time duration of the odd numbered column sub-pixels).
Dong apparently does not explicitly teach the italicized portions of:
the sub-pixels comprise a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit lights of different colors.
However, Fujii discloses “the sub-pixels comprise a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit lights of different colors”, see fig. 6 and Paras 0111 and 0116.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a method for driving a display panel by Dong with the teaching of Fujii to include a plurality of pixels that are arranged in structure in which a desired color is displayed by generated in a red pixel R, a green pixel G and a blue pixel B, as a known technique to yield a predictable result.
Regarding claim 2, Dong in view of Fujii teaches the method according to claim 1, wherein the n data lines comprise first data lines (fig. 4, the second data line103) and second data lines (fig. 4, the first data line103, Dong), one of the first data lines is connected to the first sub-pixel (fig. 4, the second data line103 connected to odd sub-pixel of the even numbered column, considered as “the first sub-pixel”, Dong) and one of the second data lines is connected to at least one of the second sub-pixel or the third sub-pixel (fig. 4, the first data line 103 connected to odd sub-pixel of the odd numbered column, considered as “the second sub-pixel”, Dong); and
wherein the turned-on time duration of the switch, which corresponds to a time period in which the first data signal is supplied to the input terminal of the demultiplexer, being the longest comprises: the turned-on time duration of the switch connected to the first data line being longer than the turned-on time duration of the switch connected to the second data line (fig. 8, Paras 0105-0108 and 0115-0116, wherein d represents acting durations of the data signals input to the first gating branch 110 and the third gating branch 112 and e represents acting durations of the data signals input to the second gating branch 111 and the fourth gating branch 113, from the drawing e is greater than d, so the time duration of the switches coupled to the even numbered column sub-pixels is longer than the time duration of the odd numbered column sub-pixels, Dong).
Regarding claim 3, Dong in view of Fujii teaches the method according to claim 2, wherein the n switches comprise first switches connected to the first data lines (fig. 4, a gating devices 114), the display panel further comprises control lines connected to control terminals of the n switches (fig. 4, MUX1-MUX4), the control lines comprise first control lines (fig. 4, MUX2), and the control terminals of the first switches are connected to a same one of the first control lines (fig. 4, MUX2); and
wherein the method further comprises: supplying by the first control line an enable signal to simultaneously turn on the first switches connected to the first control line (fig. 4, 8 and Para 0069, wherein a second data line 103 coupled to the second gating branch 111, Dong).
Regarding claim 4, Dong in view of Fujii teaches the method according to claim 3, wherein the n switches comprise first switches connected to the second data lines (fig. 4, a gating devices 114), the control lines further comprise second control lines (fig. 4, MUX1), the control terminals of the second switches are connected to a same one of the second control lines (fig. 4, 8 and Para 0069, wherein a first data line 103 coupled to the first gating branch 110, Dong); and
wherein the method further comprises:
supplying, by the second control line, an enable signal to simultaneously turn on the second switches connected to the second control line (fig. 4, 8 and Para 0069, wherein a first data line 103 coupled to the first gating branch 110, Dong),
wherein a time duration of an active level of the enable signal supplied by the first control line is longer than a time duration of an active level of the enable signal supplied by the second control line (fig. 8, Paras 0105-0108 and 0115-0116, wherein d represents acting durations of the data signals input to the first gating branch 110 and the third gating branch 112 and e represents acting durations of the data signals input to the second gating branch 111 and the fourth gating branch 113, from the drawing e is greater than d, so the time duration of the switches coupled to the even numbered column sub-pixels is longer than the time duration of the odd numbered column sub-pixels, Dong).
Regarding claim 5, Dong in view of Fujii teaches the method according to claim 2, wherein each of the sub-pixels comprises a pixel circuit, the pixel circuits are arranged in a second direction to define pixel circuit rows, and the second direction crosses the first direction(figs 2, 4 and Para 0037, wherein each sub-pixel includes a pixel circuit, Dong);
wherein the data terminal comprises a plurality of data terminals (fig. 4, Data 1 and Data2), and the demultiplexer comprises a plurality of demultiplexers (fig. 4, the first gating branch 110, the second gating branch 111, the third gating branch 112 and the fourth gating branch 113, Dong),
wherein the method further comprises:
supplying, by the plurality of data terminals, data signals to the input terminals of the plurality of demultiplexers respectively, to input a row data signal to the data lines, wherein the row data signal comprises data signals required by the pixel circuits in the pixel circuit row, and in a time period of inputting the row data signal to the data lines, in each demultiplexer, the switch connected to the first data line and the switch connected to the second data line each are turned on once (fig. 4 and Para 0069, Dong).
Regarding claim 6, Dong in view of Fujii teaches the method according to claim 2, wherein the output terminals of the demultiplexer are connected to at least one first data line of the first data lines and at least one second data line of the second data lines (fig. 4, the gating device 114 of the second gating branch 111 connected to the second data line 103 and the gating device 114 of the first gating branch 110 connected to the first data line 103, respectively, Dong), the switches comprise at least one first switch connected to the at least one first data line (fig. 4, the gating device 114 of the second gating branch 111 connected to the second data line 103, Dong), and at least one second switch connected to the at least one second data line (fig. 4, the gating device 114 of the first gating branch 110 connected to the first data line 103, respectively, Dong), and
wherein the turned-on time duration of the switch, which corresponds to a time period in which the first data signal is supplied to the input terminal of the demultiplexer, being the longest comprises: sequentially supplying, by the data terminal, the data signals to the input terminal of the demultiplexer, and turning on the first switch and the second switch in the demultiplexer in different time periods, wherein the turned-on time duration of the first switch is longer than the turned-on time duration of the second switch (fig. 8, Paras 0105-0108 and 0115-0116, wherein d represents acting durations of the data signals input to the first gating branch 110 and the third gating branch 112 and e represents acting durations of the data signals input to the second gating branch 111 and the fourth gating branch 113, from the drawing e is greater than d, so the time duration of the switches coupled to the even numbered column sub-pixels is longer than the time duration of the odd numbered column sub-pixels, Dong).
Regarding claim 7, Dong in view of Fujii teaches the method according to claim 6, wherein the first data lines comprise a first data sub-line (fig. 4, the second data line 103, Dong) and a second data sub-line (fig. 4, the second data line 104, Dong), the first data sub-line is connected to odd-numbered pixel circuits in the first pixel circuit column (see fig. 4 below), and the second data sub-line is connected to even-numbered pixel circuits in the first pixel circuit column(see fig. 4 below, Dong); and
the first switch comprises a first sub-switch connected to the first data sub-line (fig. 4, a gating device 114, controlled by MUX2, Dong) and a second sub-switch connected to the second data sub-line (fig. 4, a gating device 114, controlled by MUX4, Dong), see fig. 4 below;
wherein the second data lines comprise a third data sub-line (fig. 4, the first data line 103, Dong) and a fourth data sub-line (fig. 4, the a first data line 104, Dong), the third data sub-line is connected to odd-numbered pixel circuits in the second pixel circuit column, and the fourth data sub-line is connected to even-numbered pixel circuits in the second pixel circuit column (see fig. 4 below, Dong); and
the second switch comprises a third sub-switch connected to the third data sub-line (fig. 4, a gating device 114, controlled by MUX1, Dong) and a fourth sub-switch connected to the fourth data sub-line (fig. 4, a gating device 114, controlled by MUX3, Dong);
wherein the demultiplexer comprises the first sub-switch, the second sub-switch, the third sub-switch, and the fourth sub-switch (fig. 4, MUX1-4, see fig. 4 below);
wherein the turning on the first switch and the second switch in the demultiplexer in different time periods comprises: alternately turning on the first switch and the second switch in the demultiplexer (fig. 8);
wherein in a time period of inputting data signals to the odd-numbered pixel circuits in the first pixel circuit column and the second pixel circuit column, the first sub-switch and the third sub-switch are turned on in different time periods, and the turned-on time duration of the first sub-switch is longer than the turned-on time duration of the third sub-switch (fig. 8, Paras 0105-0108 and 0115-0116, wherein d represents acting durations of the data signals input to the first gating branch 110 and e represents acting durations of the data signals input to the second gating branch 111, from the drawing e is greater than d, so the time duration of the switches coupled to the even numbered column sub-pixels is longer than the time duration of the odd numbered column sub-pixels, Dong); and
wherein in a time period of inputting data signals to the even-numbered pixel circuits in the first pixel circuit column and the second pixel circuit column, the second sub-switch and the fourth sub-switch are turned on in different time periods, and the turned-on time duration of the second sub-switch is longer than the turned-on time duration of the fourth sub-switch (fig. 8, Paras 0105-0108 and 0115-0116, wherein d represents acting durations of the data signals input to the third gating branch 112 and e represents acting durations of the data signals input to the fourth gating branch 113, from the drawing e is greater than d, so the time duration of the switches coupled to the even numbered column sub-pixels is longer than the time duration of the odd numbered column sub-pixels, Dong); and
Dong in view of Fujii teaches wherein each of the sub-pixels comprises a pixel circuit, the pixel circuits in the first sub-pixels are arranged in the first direction to define a first pixel circuit column, the pixel circuits in the second sub-pixels and the pixel circuits in the third sub-pixels are alternately arranged in the first direction to define a second pixel circuit column (fig. 6 and Para 0116, Fujii).
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Regarding claim 8, Dong in view of Fujii teaches the method according to claim 6, wherein the first data line is connected to the pixel circuits in the first pixel circuit column (fig. 4, the second data line 103 and Para 0101, Dong), the second data line is connected to the pixel circuits in the second pixel circuit column (fig. 4, the first data line 103 and Para 0101, Dong), and the output terminals of the demultiplexer are connected to one first data line and one second data line (fig. 4 and Para 0101, Dong); and
wherein the sequentially supplying, by the data terminal, the data signals to the input terminal of the demultiplexer, and turning on the first switch and the second switch in the demultiplexer in different time periods (figs 4 and 8) comprises:
in a time period of supplying, by the data terminal, the first data signal to the input terminal of the demultiplexer, turning on the first switch to input the first data signal to the first data line (figs 4, 8 and Para 0101, wherein In a second time period t2′, the second gating branch 111 electrically connects the data signal terminal 107 to all first data lines 103 coupled to sub-pixels located in even-numbered columns, Dong); and
in a time period of supplying, by the data terminal, the second data signal to the input terminal of the demultiplexer, turning on the second switch to input the second data signal to the second data line (figs 4, 8 and Para 0101, wherein in a first time period t1′, the first gating branch 110 electrically connects the data signal terminal 107 to all first data lines 103 coupled to sub-pixels located in odd-numbered columns, so as to input the data signals output by the data signal terminal 107 to all the first data lines 103 coupled to the sub-pixels located in the odd-numbered columns, Dong); and
Dong in view of Fujii teaches wherein each of the sub-pixels comprises a pixel circuit, the pixel circuits in the first sub-pixels are arranged in the first direction to define a first pixel circuit column, the pixel circuits in the second sub-pixels and the pixel circuits in the third sub-pixels are alternately arranged in the first direction to define a second pixel circuit column (fig. 6 and Para 0116, Fujii);
Dong in view of Fujii teaches in a time period of supplying, by the data terminal, the third data signal to the input terminal of the demultiplexer, turning on the second switch to input the third data signal to the second data line (fig. 6 and Para 0120, wherein during a period in which the first selection signal CLA has a gate-on voltage the data driver 300 applies data signals corresponding to the red pixels R, and data signals corresponding to the blue pixels B to the data lines D1-Dm, Fujii).
Regarding claim 9, Dong in view of Fujii teaches the method according to claim 2, wherein the demultiplexer comprises a first demultiplexer (fig, 4, the combination of a second gating branch 111 a fourth gating branch 113, Dong) and a second demultiplexer (fig, 4, the combination of a first gating branch 110 a third gating branch 112, Dong), the switches comprise first switches connected to the first data lines (fig. 4, a gating device controlled by MUX2 and MUX4, connected to a second data line 103 and a second data line 104, Dong) and second switches connected to the second data lines (fig. 4, a gating device controlled by MUX1 and MUX3, connected to a first data line 103 and a first data line 104, Dong), the first demultiplexer comprises the first switches, the second demultiplexer comprises the second switches, the output terminals of the first demultiplexer are connected to at least two first data lines, and the output terminals of the second demultiplexer are connected to at least two second data lines (fig. 4 and Para 0055-0056, Dong); and
wherein the turned-on time duration of the switch, which corresponds to a time period in which the first data signal is supplied to the input terminal of the demultiplexer, being the longest further comprises: supplying, by the data terminal, data signals to the input terminal of first the demultiplexer, and turning on the first switches in the first demultiplexer in different time periods (figs 4, 8, Paras 0106 and 0108, Dong); and
supplying, by the data terminal, data signals to the input terminal of the second demultiplexer, and turning on the second switches in the second demultiplexer in different time periods (figs 4, 8, Paras 0105 and 0107, Dong),
wherein the turned-on time duration of the first switch is longer than the turned-on time duration of the second switch (fig. 8, Paras 0105-0108 and 0115-0116, wherein d represents acting durations of the data signals input to the third gating branch 112 and e represents acting durations of the data signals input to the fourth gating branch 113, from the drawing e is greater than d, so the time duration of the switches coupled to the even numbered column sub-pixels is longer than the time duration of the odd numbered column sub-pixels, Dong).
Regarding claim 11, Dong in view of Fujii teaches the method according to claim 1, wherein the turned-on time duration T02 of the switch, which corresponds to a time period in which the second data signal is supplied to the input terminal of the demultiplexer, is equal to the turned-on time duration T03 of the switch, which corresponds to a time period in which the third data signal is supplied to the input terminal of the demultiplexer (figs 4, 8, t’1, t’3, Paras 0105, 0107 and 0115, Dong).
Regarding claim 12, Dong in view of Fujii teaches the method according to claim 1, wherein the supplying, by the data terminal, data signals to the input terminal of the demultiplexer comprises: a time duration t1 in which the data terminal supplies the first data signal to the input terminal of the demultiplexer, a time duration t2 in which the data terminal supplies the second data signal to the input terminal of the demultiplexer, and a time duration t3 in which the data terminal supplies the third data signal to the input terminal of the demultiplexer satisfying: t1>t2, and t1>t3 (figs 4, 8, t’1, t’2 t’3, Paras 0105, 0107 and 0115-0116, Dong).
Regarding claim 13, Dong in view of Fujii teaches the method according to claim 12, wherein t2=t3 (figs 4, 8, t’1, t’3, Paras 0105, 0107 and 0115, Dong).
Regarding claim 14, Dong in view of Fujii teaches the method according to claim 12, wherein the turned-on time duration of the switch, which corresponds to the time period in which the first data signal is supplied to the input terminal of the demultiplexer, is T01, and t1 is longer than T01 (figs 4, 8, t’1, t’2 t’3, Paras 0105-0107 and 0115-0116, wherein the control data output provides the green sub-pixel data signal to the input of the demultiplexing circuit for a period greater than the period during which the first data signal is provided to the input of the demultiplexer, and the opening duration of the corresponding switch is commonly used in the art, Dong).
Regarding claim 15, Dong in view of Fujii teaches the method according to claim 12, wherein each of the sub-pixels comprises a pixel circuit, the pixel circuits are arranged in a second direction to define pixel circuit rows, and the second direction crosses the first direction(figs 2, 4 and Para 0045, Dong),
the data terminal comprises a plurality of data terminals, and the demultiplexer comprises a plurality of demultiplexers (fig. 4 and para 0069, Dong),
the method further comprises: supplying, by the plurality of data terminals, data signals to the input terminals of the plurality of demultiplexers to input a row data signal to the data lines, wherein the row data signal comprises data signals required by the pixel circuits in the pixel circuit row (fig. 6 and Para 0076, Dong),
Dong in view of Fujii teaches the wherein in a time period of inputting the row data signal to the data lines, the data terminal supplies two data signals to the input terminal of the demultiplexer, one of the two data signals is the first data signal, and the other one of the two data signals is the second data signal or the third data signal (figs 6, 7 and Para 0120, Fujii).
Regarding claim 17, Dong in view of Fujii teaches the method according to claim 1, wherein the first sub-pixel is a green sub-pixel (fig. 6 and Para 0120, Fujii).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2023/0050569), in view of Fujii (US 2014/0333676), and further in view of Zhang (US 2023/0066643).
Regarding claim 10, Dong in view of Fujii teaches the method according to claim 9, wherein the at least two first data lines comprise a first data sub-line (fig. 4, the second data line 103, Dong) and a second data sub-line (fig. 4, the second data line 104, Dong), the first data sub-line is connected to odd-numbered pixel circuits in the first pixel circuit column (fig. 4, the second gating branch 111, Dong), and the second data sub-line is connected to even-numbered pixel circuits in the first pixel circuit column (fig. 4, the fourth gating branch 113, Dong); and
the first switches comprise a first sub-switch connected to the first data sub-line (fig. 4, a gating device 114, controlled by MUX2, Dong) and a second sub-switch connected to the second data sub-line (fig. 4, a gating device 114, controlled by MUX4, Dong);
wherein the at least two second data lines comprise a third data sub-line (fig. 4, the first data line 103, Dong) and a fourth data sub-line (fig. 4, the first data line 104, Dong), the third data sub-line is connected to odd-numbered pixel circuits in the second pixel circuit column (fig. 4, the first gating branch 110, Dong), and the fourth data sub-line is connected to even-numbered pixel circuits in the second pixel circuit column ((fig. 4, the third gating branch 112, Dong)); and
the second switches comprise a third sub-switch connected to the third data sub-line (fig. 4, a gating device 114, controlled by MUX1, Dong) and a fourth sub-switch connected to the fourth data sub-line (fig. 4, a gating device 114, controlled by MUX3, Dong),
Dong in view of Fujii teaches wherein each of the sub-pixels comprises a pixel circuit, the pixel circuits in the first sub-pixels are arranged in the first direction to define a first pixel circuit column, the pixel circuits in the second sub-pixels and the pixel circuits in the third sub-pixels are alternately arranged in the first direction to define a second pixel circuit column (fig. 6 and Para 0116, Fujii);
Dong in view of Fujii does not expressly disclose the first switches in the first demultiplexer comprise two first sub-switches and two second sub-switches, and the second switches in the second demultiplexer comprise two third sub-switches and two fourth sub-switches,
wherein the turning on the first switches in the first demultiplexer in different time periods comprises:
in a time period of inputting data signals to the odd-numbered pixel circuits in the first pixel circuit column, turning on the two first sub-switches in different time periods; and
in a time period of inputting data signals to the even-numbered pixel circuits in the first pixel circuit column, turning on the two second sub-switches in different time periods, and
wherein the turning on the second switches in the second demultiplexer in different time periods comprises: in a time period of inputting data signals to the odd-numbered pixel circuits in the second pixel circuit column, turning on the two third sub-switches in different time periods; and
in a time period of inputting data signals to the even-numbered pixel circuits in the second pixel circuit column, turning on the two fourth sub-switches in different time periods.
However, Zhang discloses the first switches in the first demultiplexer comprise two first sub-switches (fig. 6, T2 and T4) and two second sub-switches (fig. 6, T6 and T8), and the second switches in the second demultiplexer comprise two third sub-switches (fig. 6, T1 and T3) and two fourth sub-switches (fig. 6, T5 and T7),
wherein the turning on the first switches in the first demultiplexer in different time periods (fig. 7) comprises:
in a time period of inputting data signals to the odd-numbered pixel circuits in the first pixel circuit column, turning on the two first sub-switches in different time periods; and in a time period of inputting data signals to the even-numbered pixel circuits in the first pixel circuit column, turning on the two second sub-switches in different time periods, and wherein the turning on the second switches in the second demultiplexer in different time periods comprises: in a time period of inputting data signals to the odd-numbered pixel circuits in the second pixel circuit column, turning on the two third sub-switches in different time periods; and in a time period of inputting data signals to the even-numbered pixel circuits in the second pixel circuit column, turning on the two fourth sub-switches in different time periods, see fig. 6, 7 and Paras 0044-0046.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace the time-division multiplexing circuit of Dong in view of Fujii with a multiplexing circuit of Zhang which includes a four thin film transistors connected to pixels located in the even numbered Columns and a four thin film transistors connected to pixels located in the odd numbered Columns which are sequentially turned on in different time, as a known technique to yield a predictable result.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dong (US 2023/0050569), in view of Fujii (US 2014/0333676), and further in view of Jeong (US 2014/0240379).
Regarding claim 16, Dong in view of Fujii teaches the method according to claim 12, But Dong in view of Fuji does not expressly disclose wherein 1<t1/t2≤2, and 1<t1/t3≤2.
However, Jeong discloses 1<t1/t2≤2, and 1<t1/t3≤2, see figs 2, 4 and Paras 0084-0085.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified a method for driving a display panel by Dong in view of Fujii with the teaching of Jeong that the signal controller outputs the first clock signal CLA, the second clock signal CLB, and the third clock signal CLC to control the first switch to the third switch to turn on for a preset period of time to write data signals to the red signal data line, the blue signal data line, and the green signal data, respectively; wherein the active period of the third clock signal CLC is more than twice the first clock signal CLA or the second clock signal CLB, a green subpixel (corresponding to the first subpixel being a green subpixel) data signal has a writing time that is more than twice as long as a writing time of a red subpixel data signal and a blue subpixel data signal (corresponding to 1 < to/t2 < 2, 1 < to/t3 < 2), as a known technique to yield a predictable result.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tang (US 2021/0295759), relates to the field of display technologies and, in particular, a driving method of a display panel, a display panel, and a display device.
Lin (US 2016/0078845), relates to a display apparatus. More particularly, the present disclosure relates to a multiplexer circuit in a display panel.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAIFELDIN E ELNAFIA whose telephone number is (571)270-5852. The examiner can normally be reached 9-5.
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/S.E.E/Examiner, Art Unit 2625 12/13/2025
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625