Prosecution Insights
Last updated: July 17, 2026
Application No. 18/735,274

MEMS DEVICE AND MANUFACTURING METHOD OF MEMS DEVICE

Non-Final OA §102
Filed
Jun 06, 2024
Priority
Dec 23, 2021 — JP 2021-209531 +1 more
Examiner
PHAM, LONG
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1515 granted / 1655 resolved
+31.5% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
38 currently pending
Career history
1688
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
9.4%
-30.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1655 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-5, 9, 14, and 15 in the reply filed on 6/3/26 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, 5, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukumitsu et al. (US pub 20180127268). With respect to claim 1, Fukumitsu et al. teach a MEMS device, comprising (see figs. 1-8, particularly fig. 7 and associated text): a first substrate 20 including a MEMS structure F3; a second substrate 30 facing the first substrate with an interval therebetween in a facing direction (vertically); a first joint portion CK, CK’ including a eutectic layer including as a main material, a eutectic alloy of a plurality of types of metal, provided between the first substrate and the second substrate and surrounding the MEMS structure as viewed in the facing direction, and being joined to the first substrate and the second substrate; a conductive contact layer H1 provided between the first substrate and the second substrate, being directly or indirectly in contact with the first substrate and directly or indirectly in contact with the second substrate, and that does not melt at a temperature at which the plurality of types of metal undergo a metal eutectic reaction (see para 0104); and a first insulating layer S3’ provided on the contact layer and being electrically insulated. With respect to claim 3, Fukumitsu et al. teach a second joint portion NK1, NK1’ including a eutectic layer including as a main material, the eutectic alloy of the plurality of types of metal, positioned inside the first joint portion as viewed in the facing direction between the first substrate and the second substrate, and being joined to the first substrate and the second substrate. See fig. 7 and associated text. With respect to claim 5, Fukumitsu et al. teach the first insulating layer S3’ is embedded in at least one of the first substrate and the second substrate 30. See fig. 7 and associated text. With respect to claim 9, Fukumitsu et al. teach the contact layer includes a portion of the plurality of types of metal (Al) included in the first joint portion. See para 0104. Allowable Subject Matter Claims 2, 4, and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a joint portion having a mixture of metal materials and a contact having a single metal material between a lower substrate and an upper substrate as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 06, 2024
Application Filed
Jul 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12685219
PACKAGE COMPRISING A CHIPLET LOCATED BETWEEN AN INTEGRATED DEVICE AND A METALLIZATION PORTION
3y 10m to grant Granted Jul 14, 2026
Patent 12685214
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
3y 7m to grant Granted Jul 14, 2026
Patent 12685213
SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR PACKAGE
3y 2m to grant Granted Jul 14, 2026
Patent 12685233
THREE-DIMENSIONAL STACKING SEMICONDUCTOR ASSEMBLIES WITH NEAR ZERO BOND LINE THICKNESS
2y 0m to grant Granted Jul 14, 2026
Patent 12677686
Electronic Package with Components Mounted at Two Sides of a Layer Stack
3y 9m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 3m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1655 resolved cases by this examiner. Grant probability derived from career allowance rate.

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