DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 thru 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoon et al. US 2018/0350818 A1 in view of Kim et al. US 2018/0226411 A1. Yoon discloses (see, for example, FIG. 22) a semiconductor device 700a comprising: a substrate 110, which includes a cell region CELL and a core region CORE/PERI; a boundary element separation film 112C (i.e. inside the interface region INTERFACE) which is placed inside the substrate 110, and separates the cell region CELL and the core region CORE/PERI; and a bit line BLS, which includes layers 156/152/150 which is placed on the cell region CELL and the boundary element separation film 112C and extends along a first direction (i.e. x-direction), wherein the boundary element separation film 112C includes a first region (i.e. left side) and a second region (i.e. right side). The bit line BLS is placed over the boundary element separation film 112C. Yoon does not disclose a separation region capping film which is placed on the boundary element separation film; and … the separation region capping film is placed on the second region of the boundary element separation film, and is not placed on the first region of the boundary element separation film, an upper side of the first region of the boundary element separation film is placed on a plane the same as that of an upper side of the separation region capping film. However, Kim discloses (see, for example, FIG. 7) a semiconductor device 400 comprising an interface region INTERFACE, which includes a separation region capping film 132 above a boundary element separation film 112C. The separation region capping film 132 is placed on the second region of the boundary element separation film 112C, and is not placed on the first region (i.e. left side) of the boundary element separation film 112C, and the upper side of the first region of the boundary element separation film 112C is placed on a plane the same as that of an upper side of the separation region capping film 132. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a separation region capping film which is placed on the boundary element separation film; and … the separation region capping film is placed on the second region of the boundary element separation film, and is not placed on the first region of the boundary element separation film, an upper side of the first region of the boundary element separation film is placed on a plane the same as that of an upper side of the separation region capping film in order to provide further support between the boundary element separation film and the overlying layers, and to improve the prevention of a short circuit between the cell region and core region.
Regarding claim 2, see, for example, FIG. 7 wherein Kim discloses the first region of the
boundary element separation film 112C being nearer to the cell region CELL than the second region of the boundary element separation film 112C.
Regarding claim 3, see, for example, FIG. 7 wherein Kim discloses the boundary element separation film 112C further includes a third region (i.e. farthest right side), the second region of the boundary element separation film 112C being placed between the first region (i.e. left side wherein there is no separation region capping film 132) of the boundary element separation film 112C and the third region of the boundary element separation film 112C, and a height of the upper side of the first region (i.e. left side wherein there is no separation region capping film 132) and an upper side of the third region (farthest right side) of the boundary element separation film 112C being higher than a height of an upper side of the second region (i.e. the middle region of the boundary element separation film 112C where the separation region capping film 132 is placed) of the boundary element separation film 112C.
Regarding claim 4, see, for example, FIG. 22 wherein Yoon discloses a buffer layer
MIP2.
Regarding claim 5, see, for example, FIG. 22 wherein Yoon discloses a bit line capping
film 170.
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Eugene Lee
June 20, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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