Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of
the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yamachi (WO 2022044797, hereinafter Yamachi).
With respect to claim 1, Yamachi disclose a transistor (Page 02; Abstract - transistor), comprising:
a gate (15 of Fig. 21);
a gate insulating layer (171) between the gate and the substrate (Fig. 21 – 171 is between 15 and 10); and a first insulating pattern (172 & 173) between the gate insulating layer and a substrate (substrate10 - 172 & 173 is between 171 & 10), wherein the gate comprises: a pair of poles (152& 153); and a connecting portion (151) that connects the paired poles (151 connects 152&153), and wherein the first insulating pattern is between the poles (172 & 173 is between 152&153).
In the same embodiment Yamachi does not explicitly disclose an n-type source region below the gate; an n-type drain region adjacent to the gate; and the pair of poles extends to the source region.
In another embodiment, Yamachi discloses an n-type source region below the gate (Page 04, Para 04 – n-type source region 19 ); an n-type drain region (Page 04; Para 04 – n-type drain region 21) adjacent to the gate (Fig. 2); and the pair of poles extends to the source region (Fig. 21 – source region is provided in the substrate and 152&153 extends into it). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s first embodiment by having disclosure from second embodiment in order improve switching capability and current flow of the transistor.
With respect to claim 3, Yamachi discloses wherein the first insulating pattern comprises SixNy, where X and y are real numbers greater than 0 (Page 07; Para 01-02 – SiN).
With respect to claim 8, Yamachi discloses wherein the first insulating pattern is a single or composite layer, which is formed of at least one of SiON, SiONC, SiO₂, or SiOC (Page 07; Para 02 – Silicon oxide).
With respect to claim 9, Yamachi discloses wherein the first insulating pattern comprises a void (Fig. 21 – there is a void between 172 & 173).
With respect to claim 10, Yamachi discloses an etch stop layer, which is placed on the substrate adjacent to the gate and coplanar with the first insulating pattern (Page 07 – Para 03 – resist pattern; Page 08 – Para 02; Page 09, Para 01).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamachi in view of Roy (US 2018/0061875, hereinafter Roy).
With respect to claim 2, Yamachi does not explicitly disclose wherein a thickness of the first insulating pattern is in a range from 5 nm to 50 nm.
In an analogous art, Roy discloses wherein a thickness of the first insulating pattern is in a range from 5 nm to 50 nm (Para 0025).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having Roy’s disclosure in order to isolate different components to avoid electrical shorts in a semiconductor device.
Claims 5-6, are rejected under 35 U.S.C. 103 as being unpatentable over Yamachi in view of KR (KR 102454575, hereinafter KR).
With respect to claim 5, Yamachi does not explicitly disclose wherein a depth of the pole is in a range from 200 nm to 500 nm, when measured from a surface of the substrate.
In an analogous art, KR discloses wherein a depth of the pole is in a range from 200 nm to 500 nm, when measured from a surface of the substrate (Page 08; last Para – 100 angstrom to 10,000 angstroms (10nm -1000nm)). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having KR’s disclosure in order to achieve the optimal results.
With respect to claim 6, Yamachi discloses wherein an aspect ratio of the pole is in a range from 1 to 10 (Fig. 21 – 152/153 – length and width ratio of 152/153 is from 1 to 5).
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yamachi in view of Reznicek et al. (US 2022/0085013, hereinafter Reznicek).
With respect to claim 4, Yamachi discloses the transistor of claim 1.
Yamachi does not explicitly disclose wherein a width of the pole is in a range from 50 nm to 200 nm, when measured at a surface level of the substrate.
In an analogous art, Reznicek discloses wherein a width of the pole is in a range from 50 nm to 200 nm, when measured at a surface level of the substrate (Para 0078 – 100nm). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having Reznicek’s disclosure in order to achieve the optimal performance of the semiconductor device.
With respect to claim 7, Yamachi/Reznicek discloses the transistor of claim 4.
Yamachi does not explicitly disclose wherein a distance between the poles is in a range from 10 nm to 80 nm, when measured at a surface level of the substrate.
In an analogous art, Reznicek discloses wherein a distance between the poles is in a range from 10 nm to 80 nm, when measured at a surface level of the substrate (Para 0078; 10-30nm).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having Reznicek’s disclosure in order to achieve the optimal performance of the semiconductor device.
Claim 25, 29-30 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Yamachi in view of Yang et al. (US 2023/0317760, hereinafter Yang).
With respect to claim 25, Yamachi discloses an image sensing device (Page 13; Para 01), comprising: a first substrate (301 of Fig. 16) including a photodiode region (PD - Page 13; Para 01 – photodiode), a transfer transistor (TR), and a floating diffusion region (Page 13; Para 02 – floating diffusion), the transfer transistor comprising a gate (15 of Fig. 21) including a pair of poles (152 & 153), which are extended to an n-type region of the photodiode (Page 16 & 17; Para 01; Fig. 21 – source region is provided in the substrate and 152&153 extends into it), and a connecting portion (151), which connect the poles of the pair of poles to each other (151 connects 152 & 153), and a first insulating pattern (172 & 173) between the poles of the pair of poles (172 & 173 is between 152&153); a source follower transistor (page 15; Para 03 – source follower); and a logic circuit (108 of Fig. 12).
Yamachi does not explicitly disclose a second substrate that includes the source follower and a third substrate includes the logic circuit, wherein the floating diffusion region of the first substrate is electrically connected to a gate of the source follower transistor of the second substrate.
In an analogous art, Yang discloses a second substrate (820 of Fig. 10) that includes the source follower (Para 0036) and a third substrate (830) includes the logic circuit (Para 0036), wherein the floating diffusion region of the first substrate (304) is electrically connected to a gate of the source follower transistor of the second substrate (Para 0016 – the floating diffusion region is couple to the gate of the source follower transistor). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having Yang’s disclosure in order to connect different components of a semiconductor device to perform the desired task.
With respect to claim 29, Yamachi/Yang discloses the image sensing device of claim 25.
Yamachi does not explicitly disclose wherein the floating diffusion region of the first substrate is connected to the gate of the source follower transistor of the second substrate through a via, which penetrates the second substrate.
In an analogous art, Yang discloses wherein the floating diffusion region of the first substrate is connected to the gate of the source follower transistor of the second substrate through a via, which penetrates the second substrate (Fig. 10 - first substrate is connected to second substrate though a via, wherein the via penetrates the second substrate). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having Yang’s disclosure in order to connect different components of a semiconductor device to perform the desired task.
With respect to claim 30, Yamachi/Yang discloses the image sensing device of claim 29.
Yamachi does not explicitly disclose wherein a front surface of the third substrate is connected to a front surface of the second substrate.
In an analogous art, Yang discloses wherein a front surface of the third substrate is connected to a front surface of the second substrate (Fig. 10, Para 0026; 0039 – front surface of 830 is connected to front surface of 820). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having Yang’s disclosure in order to connect different components of a semiconductor device to perform the desired task.
With respect to claim 33, Yamachi/Yang discloses the image sensing device of claim 29.
Yamachi does not explicitly disclose wherein the first substrate comprises metal lines provided in a double layered structure.
In an analogous art, Yang discloses wherein the first substrate comprises metal lines provided in a double layered structure (Fig. 10 – metal lines in 304). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having Yang’s disclosure in order to connect different components of a semiconductor device to perform the desired task.
Claims 26-27 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Yamachi/Yang in view of Azuhata (US 2023/0049629, hereinafter Azuhata).
With respect to claim 26, Yamachi/Yang discloses the image sensing device of claim 25.
Yamachi/Yang does not explicitly disclose wherein the floating diffusion region of the first substrate is connected to the gate of the source follower transistor of the second substrate in a Cu-Cu bonding manner.
In an analogous art, Azuhata discloses wherein the floating diffusion region of the first substrate is connected to the gate of the source follower transistor of the second substrate in a Cu-Cu bonding manner (Para 0174 – Cu-Cu bonding). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi/Yang’s device by having Azuhata’s disclosure in order to improve the electrical conductivity and miniaturize the semiconductor device.
With respect to claim 27, Yamachi/Yang/Azuhata discloses the image sensing device of claim 26.
Yamachi does not explicitly disclose wherein a front surface of the third substrate is connected to a rear surface of the second substrate.
In an analogous art, Yang discloses wherein a front surface of the third substrate is connected to a rear surface of the second substrate (front surface of 830 is connected to rear surface of 820).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi’s device by having Yang’s disclosure in order to connect different components of a semiconductor device to perform the desired task.
With respect to claim 32, Yamachi/Yang/Azuhata discloses the image sensing device of claim 30.
Yamachi/Yang does not explicitly disclose wherein the second substrate and the third substrate are connected to each other in a Cu-Cu bonding manner.
In an analogous art, Azuhata discloses wherein the second substrate and the third substrate are connected to each other in a Cu-Cu bonding manner (Para 0174 – Cu-Cu bonding). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi/Yang’s device by having Azuhata’s disclosure in order to improve the electrical conductivity and miniaturize the semiconductor device.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Yamachi/Yang/Azuhata in view of Lin et al. (US 2020/0381465, hereinafter Lin).
With respect to claim 28, Yamachi/Yang/Azuhata discloses the image sensing device of claim 26.
Yamachi/Yang/Azuhata does not explicitly disclose a via that penetrates a rear surface of the third substrate; and an I/O pad connected to the via.
In an analogous art, Lin discloses a via that penetrates a rear surface of the third substrate (Para 0042); and an I/O pad connected to the via (Para 0057).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi/Yang/Azuhata’s device by having Lin’s disclosure in order to provide electrical connections between different component of a semiconductor device.
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Yamachi/Yang in view of Lin.
With respect to claim 31, Yamachi/Yang discloses the image sensing device of claim 29.
Yamachi/Yang/Azuhata does not explicitly disclose a via that penetrates a rear surface of the third substrate; and an I/O pad connected to the via.
In an analogous art, Lin discloses a via that penetrates a rear surface of the third substrate (Para 0042); and an I/O pad connected to the via (Para 0057).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi/Yang’s device by having Lin’s disclosure in order to provide electrical connections between different component of a semiconductor device.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Yamachi/Yang/Azuhata in view of Fujii et al. (US 2018/0233435, hereinafter Fujii).
With respect to claim 34, Yamachi/Yang/Azuhata discloses the image sensing device of claim 26.
Yamachi/Yang/Azuhata does not explicitly disclose a dummy bonding pad that connects the first substrate to the second substrate.
In an analogous art, Fujii discloses a dummy bonding pad that connects the first substrate to the second substrate (Para 0019; 0062; Fig. 2C).
Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yamachi/Yang/Azuhata’s device by having Fujii’s disclosure in order to provide srutcural support and manufacturing consistency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
Prosecution Insights