DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species (a1) fig. 2A and species (b1) figs. 1 & 6. claims 1-20, in the reply filed on 8/7/26 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 19, the limitation “wherein the upper surface of the first capacitor faces a lower surface of the second capacitor” is indefinite.
Claim 19 recites:
“wherein the first capacitor includes a first contact pad disposed on an upper surface of the first capacitor and bonded to the redistribution layer,…and the second capacitor includes a second contact pad disposed on the lower surface of the second capacitor and bonded to the interposer”.
The upper surface of the first capacitor participates in bonding with the redistribution layer and the lower surface of the second capacitor participates in bonding with the interposer. It seems that the surfaces free to face each other are the lower surface of the first capacitor and the upper surface of the second capacitor.
Claim 2 recites limitations similar to claim 19, so a similar rejection applies.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 11-13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al., KR 20150098734 A (see attached English machine translation) in view of Baek et al., KR 101982061 B1 (see attached English machine translation).
Shin teaches:
1. (see fig. 1, also see fig. 4) A method of manufacturing a semiconductor package, including a package substrate (102) and an interposer (200), the method comprising:
providing a first capacitor (108) and a semiconductor chip (104) on an upper surface of the package substrate and…;
bonding the interposer (200) and the package substrate (102) so that the upper surface of the package substrate faces the lower surface of the interposer;
forming an insulating filler (110) configured to seal the first capacitor…See Shin at English machine translation pages 2-5.
Shin does not expressly teach:
providing a second capacitor on a lower surface of the interposer;
forming an insulating filler configured to seal…the second capacitor.
In an analogous art, Baek teaches:
providing a second capacitor (200’A) to face a first capacitor (200’B)
forming an insulating filler (230a/230b) configured to seal the first capacitor and the second capacitor. See Baek at English machine translation pages 17-20.
It would have been obvious to a person of ordinary skill in the art to modify the teachings of Shin with the teachings of Baek to form “a second capacitor on a lower surface of the interposer; and an insulating filler configured to seal the first capacitor and the second capacitor” because “…it is possible to reduce the influence of the electromagnetic wave that increases as the distance between the components increases.” See Baek at page 10.
Regarding claim 2:
Baek further teaches:
2. The method of claim 1, wherein in the bonding the interposer and the package substrate, a lower surface of the first capacitor (200B’) faces an upper surface of the second capacitor (200’A), figs. 15-16.
Regarding claim 3:
Baek further teaches:
3. The method of claim 1, wherein the first capacitor (200’B) and the second capacitor (200’A) are insulated (230a/230b) from each other, figs. 15-16.
Regarding claim 4:
Baek further teaches:
4. The method of claim 1, wherein in the bonding the interposer and the package substrate,
the first capacitor (200’B) and the second capacitor (200’A) are aligned in a vertical direction, and
further comprising forming an adhesive film (240) between the first capacitor and the second capacitor, figs. 15-16, page 18.
Regarding claim 5:
Baek is silent the adhesive film includes a non-conductive adhesive film.
However, it would have been obvious to one having ordinary skill in the art to include a non-conductive adhesive film, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Regarding claim 6:
Shin further teaches:
6. The method of claim 1, wherein in providing the first capacitor and the semiconductor chip on the upper surface of the package substrate and providing the second capacitor on the lower surface of the interposer,
the package substrate does not provide a capacitor on a lower surface of the package substrate (e.g. In Shin’s figs. 1 and 4 there are no capacitors 108 on a lower surface of package substrate 102.)
Regarding claim 7:
Baek further teaches:
7. The method of claim 1, wherein at least one of the first capacitor or the second capacitor includes at least one of a silicon capacitor, a low inductance ceramic capacitor (LICC), or a multilayer ceramic capacitor (MLCC) (e.g. see MLCC at page 3)
Regarding claim 11:
Shin and Baek teach the limitations as applied to claim 1 above.
Shin further teaches the added limitation:
(see figs. 1 and 4) providing a first conductive connector (112) on an upper surface of the package substrate (102);
providing a second conductive connector (208) on a lower surface of the interposer (200);
wherein in bonding the interposer (200) and the package substrate (102), a conductive connector (112+208) is formed by combining the first conductive connector (112) and the second conductive connector (208). See Shin at pages 17-20.
Regarding claim 12:
Shin further teaches:
12. The method of claim 11, wherein a vertical length of the conductive connector (112+208) is greater than a vertical length of the semiconductor chip (104), figs. 1 and 4.
Regarding claim 13:
Baek further teaches:
13. The method of claim 11, wherein
the first capacitor (200’B) includes a first contact pad (222T) disposed on an upper surface of the first capacitor and bonded to a package substrate, and
the second capacitor (200’A) includes a second contact pad (222T) disposed on a lower surface of the second capacitor and bonded to the interposer.
the first capacitor (200’B) includes a first contact pad (222T) disposed on an upper surface of the first capacitor and bonded to a package substrate (171/140), and
the second capacitor (200’A) includes a second contact pad (222T) disposed on a lower surface of the second capacitor…, figs. 15-16, page 18.
One of ordinary skill in the art modifying Shin with Baek would form the second contact pad “bonded to the interposer” because Baek teaches the second contact pad (222T) of the second capacitor (200’A) is bonded to an upper substrate (171/152/153) in fig. 16.
Regarding claim 19:
Shin and Baek teach the limitations as applied to claims 1, 3, 11 and 13 above.
Shin further teaches the added limitation of “a redistribution layer” because the package substrate (102) has metallization on the top surface. Also see redistribution layer annotated in fig. 1 below.
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It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Baek because “In the first through third passive components 200A, 200B, and 200C, the first through third passive components 221, 222, and 223 are coupled by the resin portion 230 so that they are arranged closer to each other . Therefore, it is possible to reduce the influence of the electromagnetic wave that increases as the distance between the components increases. ” See Baek at page 10.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Baek, as applied to claim 1 above, in further view of Yeom, US Publication No. 2014/0103516 A1.
Regarding claim 8:
Shin and Baek teach all the limitations of claim 1 above, and Shin further teaches:
further comprising bonding an upper semiconductor package (300) including a chip (e.g. see top chip annotated in fig. 1 above) to the interposer (200), fig. 1.
Shin and Baek are silent:
the semiconductor chip is a logic chip, and
further comprising bonding an upper semiconductor package including a memory chip to the interposer.
In an analogous art, Yeom teaches:
(see fig. 1A) the semiconductor chip (120) is a logic chip, and
further comprising bonding an upper semiconductor package (320a, 320b) including a memory chip to the interposer (200). See Yeom at para. [0039] – [0054].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Yeom (i) in order to combine a logic chip with a memory chip in order to form an integrated memory device (e.g. memory card, para. [0070] – [0075]); and (ii) The memory chips are disposed over the logic chips has the “…the advantage that the memory chip is smaller in size than the logic chip, such that the number of the memory chips may not be reduced.” (e.g. para. [0053])
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Baek, as applied to claim 1 above, in further view of Chiu et al., US 20180047711 A1
Regarding claims 9 and 10:
Shin does not expressly teach:
wherein a sum of a vertical length of the first capacitor and a vertical length of the second capacitor is greater than a vertical length of the semiconductor chip;
wherein the vertical length of each of the first capacitor and the second capacitor is in a range of 50 μm to 100 μm.
However, Baek teaches the vertical length of the capacitors is a result effective variable in the disclosure “The plurality of passive components 221 to 225 may have various sizes and heights depending on performance, capacity, and the like.” See Baek at page 9.
It would have been obvious to one having ordinary skill in the art to form “the vertical length of each of the first capacitor and the second capacitor is in a range of 50 μm to 100 μm” since where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. See MPEP § 2144.05, Obviousness of Ranges and Optimization of Ranges. (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
In an analogous art, Chiu teaches:
(see fig. 4a) wherein a vertical length of a first capacitor (23) is greater than a vertical length of the semiconductor chip (20), para. [0036].
It would have been obvious to one of ordinary skill in the art to modify Shin’s fig. 1 to form “a sum of a vertical length of the first capacitor and a vertical length of the second capacitor is greater than a vertical length of the semiconductor chip” because:
Baek, in figs. 1 and 4, teaches wherein a sum of a vertical length of the first capacitor and a vertical length of the second capacitor fills the height between the package substrate (140/171) and an upper substrate (172/152/153); and
Chiu teaches “Therefore, by maintaining the height and size of the passive elements, the present disclosure overcomes the conventional drawbacks of poor electrical connection quality, poor coplanarity and tilted bonding.” See Chiu at para. [0017].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Baek because “In the first through third passive components 200A, 200B, and 200C, the first through third passive components 221, 222, and 223 are coupled by the resin portion 230 so that they are arranged closer to each other . Therefore, it is possible to reduce the influence of the electromagnetic wave that increases as the distance between the components increases. ” See Baek at page 10.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Chiu because “Therefore, by maintaining the height and size of the passive elements, the present disclosure overcomes the conventional drawbacks of poor electrical connection quality, poor coplanarity and tilted bonding.” See Chiu at para. [0017].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Baek, as applied to claim 11 above, in further view of Patil et al., US 20200381405 A1.
Regarding claim 14:
Shin further teaches:
14. The method of claim 11, wherein
the package substrate (102) includes chip connection bumps (106) that provide an electrical path between the semiconductor chip (104) and the package substrate, figs. 1 and 4.
Shin does not expressly teach:
capacitor connection bumps that provide an electrical path between the first capacitor and the package substrate,
wherein each of the capacitor connection bumps is smaller than each of the chip connection bumps.
In an analogous art, Patil teaches:
(see fig. 1) capacitor connection bumps (e.g. bumps directly below 112) that provide an electrical path between the first capacitor (112) and the package substrate (106). See Patil at para. [0027] – [0032].
It would have been obvious to one of ordinary skill in the art modifying Shin with Patil to form capacitor connection bumps to form the capacitor connection bumps to be smaller than each of the chip connection bumps because in Shin’s fig. 1 the capacitor 108 is much smaller in size than the chip 104.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Patil because “The passive device may be a discrete electrical component designed to improve the power delivery to the second package, for example, by reducing a voltage drop of power rails seen at the second package. As an example, the passive device may be a capacitor configured to reduce a voltage drop between the first redistribution layers and the second package.” See Patil at para. [0031].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Baek and Patil, as applied to claim 11 above, in further view of Endo et al., US Publication No. 2004/0056341 A1
Regarding claim 15:
Shin, Baek and Patil teach all the limitations of claim 11 above, and Shin further teaches:
15. The method of claim 14, wherein in providing the first capacitor (108), the semiconductor chip (104), and the first conductive connector (112) on the upper surface of the package substrate (102), and providing t the second conductive connector (208) on the lower surface of the interposer (200), and
One of ordinary skill in the art modifying Shin with Baek would form “the second capacitor on the lower surface of the interposer” because Baek teaches the second capacitor (200’A) is bonded to the lower surface of an upper substrate (172/152/153) in fig. 16.
Shin, Baek and Patil do not expressly teach:
further comprising providing an underfill material layer between the first capacitor and the package substrate and covering the capacitor connection bumps.
In an analogous art, Endo teaches (see fig. 5) an underfill material layer (18) between the first capacitor (16) and the package substrate (11) and covering the capacitor connection bumps (17), para. [0073].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Endo because the underfill helps to “shield and protect the bonded portions from the atmosphere”. See Endo at para. [0073].
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Baek, as applied to claim 1 above, in further view of Patil et al., US Publication No. 2020/0381405 A1 and Zhuang et al., US Publication No. 2017/0256508 A1.
Regarding claims 16-18:
Shin and Baek teach all the limitations of claim 11 above, and Shin further teaches:
wherein the package substrate includes:
a substrate base (102);
first upper pads (e.g. electrodes directly under 112) on an upper surface of the substrate base and connected to the first conductive connector (112);
an upper protective layer (e.g. top insulating layer of 102) covering the upper surface of the substrate base, the upper protective layer including first openings exposing the first upper pads (e.g. electrodes directly under 112), fig. 1.
Shin and Baek do not expressly teach
wherein the package substrate includes:
a substrate base;
first upper pads on an upper surface of the substrate base and connected to the first conductive connector;
second upper pads on the upper surface of the substrate base and connected () to the first capacitor; and
an upper protective layer covering the upper surface of the substrate base, the upper protective layer including first openings exposing the first upper pads and second openings exposing the second upper pads, and
wherein a horizontal width of each of the first openings is greater than a horizontal width of each of the second openings;
wherein
the package substrate further includes third upper pads on the upper surface of the substrate base and connected to the semiconductor chip,
the upper protective layer further includes third openings exposing the third upper pads, and
a horizontal width of each of the third openings is greater than the horizontal width each of the second openings;
wherein
the horizontal width of the first openings ranges from 100 μm to 200 μm, and the horizontal width of the second openings ranges from 10 μm to 100 μm.
In an analogous art, Patil teaches:
(see fig. 1) wherein the package substrate (106) includes:
a substrate base (e.g. bottom dielectric layer of 106);
first upper pads (e.g. metallization directly below 116) on an upper surface of the substrate base and connected to the plurality of conductive connectors (116);
second upper pads (e.g. metallization directly below 112) on the upper surface of the substrate base and connected to the first capacitor (112); and
an upper protective layer (e.g. top dielectric layer of 106) covering the upper surface of the substrate base, the upper protective layer including first openings exposing the first upper pads (e.g. metallization directly below 116) and second openings exposing the second upper pads (e.g. metallization directly below 112);
the package substrate further includes third upper pads (e.g. metallization directly below 110) on the upper surface of the substrate base and connected to the semiconductor chip (110),
the upper protective layer (e.g. top dielectric layer of 106) further includes third openings exposing the third upper pads (e.g. metallization directly below 110). See Patil at para. [0027] – [0032].
In an analogous art, Zhuang teaches:
(see fig. 14) wherein the package substrate (46/48/44/401/402) includes:
a substrate base (46);
first upper pads (44) on an upper surface of the substrate base and connected to the plurality of conductive connectors (210);
second upper pads (401) on the upper surface of the substrate base…; and
an upper protective layer (48) covering the upper surface of the substrate base, the upper protective layer including first openings (e.g. openings over 44) exposing the first upper pads (44) and second openings (e.g. openings over 401) exposing the second upper pads (401), and
wherein a horizontal width of each of the first openings (e.g. openings over 44) is greater than a horizontal width of each of the second openings (e.g. openings over 401);
the package substrate further includes third upper pads (402) on the upper surface of the substrate base and connected to the semiconductor chip (10),
the upper protective layer (48) further includes third openings (e.g. openings over 402) exposing the third upper pads, and
a horizontal width of each of the third openings (e.g. openings over 402) is greater than the horizontal width each of the second openings (e.g. openings over 401). See Zhuang at para. [0056] – [0059].
Patil and Zhuang are silent wherein the horizontal width of the first openings ranges from 100 μm to 200 μm, and the horizontal width of the second openings ranges from 10 μm to 100 μm.
However, absent any disclosure by the Applicant that “the horizontal width of the first openings ranges from 100 μm to 200 μm, and the horizontal width of the second openings ranges from 10 μm to 100 μm” is critical or provides for unexpected results, such a width can be considered within the skill level of one of ordinary skill in the art or by the guidance provided by Patil and Zhuang.
See MPEP § 2144.05, Obviousness of Ranges:
“Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical.” (Emphasis added.)
In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)…Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions. (Emphasis added.)
Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent").
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Patil because “The passive device may be a discrete electrical component designed to improve the power delivery to the second package, for example, by reducing a voltage drop of power rails seen at the second package. As an example, the passive device may be a capacitor configured to reduce a voltage drop between the first redistribution layers and the second package.” See Patil at para. [0031].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Zhuang to form “a horizontal width of each of the first openings is greater than a horizontal width of each of the second openings; and a horizontal width of each of the third openings is greater than the horizontal width each of the second openings” because (i) “…a risk of short circuit is low because…the RDL…will not generally contact one or both of the two rows of the first bump pads…Therefore, a length of a circuit path of the RDL… (and its impedance) can be significantly reduced. In other words, this embodiment is beneficial to yield a performance-improved circuitry.” (e.g. para. [0057]); and (ii) “The bumps..are cylindrical. The sizes and positions of the bumps…correspond to the sizes and positions of the bump pads…” (e.g. para. [0056])
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Baek, as applied to claim 19 above, in further view of Patil et al., US Publication No. 2020/0381405 A1.
Regarding claim 20:
Shin and Baek teach all the limitations of claim 19 above and Shin further teaches:
20. The method of claim 19, wherein the redistribution layer includes (see fig. 1 annotated above):
insulating layers (e.g. insulating layer overlying conductive layers/electrodes);
redistribution patterns (e.g. conductive layers/electrodes) extending in a horizontal direction within the insulating layers;
Shin does not expressly teach:
redistribution vias connected to at least one of the redistribution patterns and extending in a vertical direction within the insulating layers; and
first and second redistribution pads on the insulating layers and connected to at least one of the redistribution vias.
In an analogous art, Patil teaches:
where in the redistribution layer (106) includes (see fig. 1):
insulating layers (e.g. dielectric layers of 106),
redistribution patterns (e.g. lower level horizontal portions of metallization in 106) extending in a horizontal direction within the insulating layers;
redistribution vias (e.g. lower level vertical portions of metallization in 106) connected to at least one of the redistribution patterns (e.g. lower level horizontal portions of metallization in 106) and extending in a vertical direction within the insulating layers; and
first and second redistribution pads (e.g. topmost level horizontal portions of metallization in 106) on the insulating layers and connected to at least one of the redistribution vias (e.g. lower level vertical portions of metallization in 106). See Patil at para. [0027] – [0032].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Shin with the teachings of Patil because “The passive device may be a discrete electrical component designed to improve the power delivery to the second package, for example, by reducing a voltage drop of power rails seen at the second package. As an example, the passive device may be a capacitor configured to reduce a voltage drop between the first redistribution layers and the second package.” See Patil at para. [0031].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
9 October 2026
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