Prosecution Insights
Last updated: October 02, 2026
Application No. 18/735,435

SEMICONDUCTOR MANUFACTURING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, AND SEMICONDUCTOR APPARATUS

Non-Final OA §102§103
Filed
Jun 06, 2024
Priority
Oct 25, 2023 — JP 2023-183559
Examiner
LEE, DA WEI
Art Unit
Tech Center
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
37 granted / 46 resolved
+20.4% vs TC avg
Strong +15% interview lift
Without
With
+15.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
22 currently pending
Career history
82
Total Applications
across all art units

Statute-Specific Performance

§103
59.9%
+19.9% vs TC avg
§102
31.6%
-8.4% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 46 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 6, 8, 9, 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakaoka ( Pub. No. JP H02288241 A ), hereinafter Nakaoka. PNG media_image1.png 781 1429 media_image1.png Greyscale Regarding Independent Claim 6, Nakaoka teaches a method of manufacturing a semiconductor apparatus comprising: a step of discharging resin paste ( Nakaoka, FIG. 1, 4; FIG. 2(c), FIG. 2(d), 41; page 3, line 34, a conductive adhesive 4 ) to a range including a center of a cross-shaped block ( Nakaoka, FIG. 2, FIG. 3, 41 ) formed on a die pad ( Nakaoka, FIG. 1(a), 2; FIG. 2, FIG. 3, 2; page 4, line 21, die pad 2 ) and not including ends of the block; and a step of placing a semiconductor device ( Nakaoka, FIG. 3, 6; page 4, line 22, semiconductor chip 6 ), which is a quadrangle in plan view, on an upper surface of the block ( Nakaoka, FIG. 2, FIG. 3, 41 ) such that vertexes of the quadrangle and ends of a cross of the block coincide to bond the die pad ( Nakaoka, FIG. 1(a), 2; FIG. 2, FIG. 3, 2 ) and the semiconductor device ( Nakaoka, FIG. 3, 6 ) with the resin paste ( FIG. 3, 41 ) ( Nakaoka, page 4, line 21, First, FIG. 3(a) shows a state in which the conductive adhesive 41 is applied onto the die pad 2, and is applied in the shape of two intersecting lines. Next, in FIG. 3(b), the semiconductor chip 6 is transferred above the conductive adhesive 41, and the conductive adhesive 41 is slightly expanded by the weight of the semiconductor chip 6. Thereafter, in FIG. 3(e) ( ps. this should be FIG. 3(c) ), the semiconductor chip 6 is pressurized from above, so that the conductive adhesive 41 is uniformly spread over the entire back surface of the semiconductor chip 6 without generating bubbles. This pressurizing force may be about 30g ). Regarding Independent Claim 8, Nakaoka teaches a semiconductor apparatus comprising: a die pad ( Nakaoka, FIG. 1(a), 2; FIG. 2, FIG. 3, 2; page 4, line 21, die pad 2 ) including a cross-shaped block ( Nakaoka, FIG. 2, FIG. 3, 41 ) on an upper surface; and a semiconductor device ( Nakaoka, FIG. 3, 6; page 4, line 22, semiconductor chip 6 ) bonded to the block by resin paste ( Nakaoka, FIG. 1, 4; FIG. 2(c), FIG. 2(d), 41; page 3, line 34, a conductive adhesive 4 ), wherein the semiconductor device ( Nakaoka, FIG. 3, 6 ) is a quadrangle in plan view and is bonded such that vertexes of the quadrangle of the semiconductor device ( ( Nakaoka, FIG. 3, 6 ) and ends of a cross ( Nakaoka, FIG. 2, FIG. 3, 41 ) of the block coincide ( Nakaoka, FIG. 3, 6 ) with the resin paste ( FIG. 3, 41 ) ( Nakaoka, page 4, line 21, First, FIG. 3(a) shows a state in which the conductive adhesive 41 is applied onto the die pad 2, and is applied in the shape of two intersecting lines. Next, in FIG. 3(b), the semiconductor chip 6 is transferred above the conductive adhesive 41, and the conductive adhesive 41 is slightly expanded by the weight of the semiconductor chip 6. Thereafter, in FIG. 3(e) ( ps. this should be FIG. 3(c) ), the semiconductor chip 6 is pressurized from above, so that the conductive adhesive 41 is uniformly spread over the entire back surface of the semiconductor chip 6 without generating bubbles. This pressurizing force may be about 30g ). Regarding Independent Claim 9, Nakaoka teaches a semiconductor apparatus comprising: a die pad ( Nakaoka, FIG. 1(a), FIG. 2, FIG. 3, 2; page 4, line 21, die pad 2 ); and a semiconductor device ( Nakaoka, FIG. 3, 6; page 4, line 22, semiconductor chip 6 ) bonded ( Nakaoka, page 4, lines 21 – 27 ) to the die pad ( Nakaoka, FIG. 1(a), FIG. 2, FIG. 3, 2 ) by resin paste ( Nakaoka, FIG. 1, 4; FIG. 2(c), FIG. 2(d), 41; page 3, line 34, a conductive adhesive 4 ), four sides of the semiconductor device ( Nakaoka, FIG. 3, 6 ) forming a quadrangle in plan view, wherein the die pad ( Nakaoka, FIG. 1(a), FIG. 2, FIG. 3, 2 ) includes, on a surface to which the semiconductor device is bonded, four grooves ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9; page 3, line 35, a recess 9 in which two grooves intersect on the bottom surface ) extending along the respective sides, and the grooves ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9; page 3, line 35, a recess 9 in which two grooves intersect on the bottom surface ) are present ( Nakaoka, FIG. 3 ) in centers of the sides in plan view and are absent ( Nakaoka, FIG. 3 ) at both ends of the sides. Regarding Claim 10, Nakaoka teaches the semiconductor apparatus as claimed in claim 9, on which this claim is dependent, Nakaoka further teaches: wherein length of the grooves ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9 ) is half of length of the sides, and the grooves ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9 ) are formed in equal ( Nakaoka, FIG. 3(3)-2, X shape of 41 is equally positioned from sides ) positions from both ends of the sides. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nakaoka, in view of Nakaoka. Regarding Independent Claim 7, Nakaoka teaches a method of manufacturing a semiconductor apparatus comprising: a step of forming a die pad ( Nakaoka, FIG. 1(a), 2; FIG. 2, FIG. 3, 2; page 4, line 21, die pad 2 ) including, on an upper surface, four grooves ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9; page 3, line 35, a recess 9 in which two grooves intersect on the bottom surface ) extending along respective sides of a quadrangle; a step of discharging resin paste ( Nakaoka, FIG. 1, 4; FIG. 2(c), FIG. 2(d), 41; page 3, line 34, a conductive adhesive 4 ); and a step of placing a semiconductor device ( Nakaoka, FIG. 3, 6; page 4, line 22, semiconductor chip 6 ), which is a quadrangle in plan view, on the upper surface of the die pad ( Nakaoka, FIG. 1(a), 2; FIG. 2, FIG. 3, 2 ) such that vertexes of the quadrangle formed by the semiconductor device ( Nakaoka, FIG. 3, 6 ) and vertexes of the quadrangle formed by the four grooves ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9; FIG. 3(a)-2 ) coincide to bond ( Nakaoka, page 4, lines 21 – 27 ) the die pad ( Nakaoka, FIG. 1(a), 2; FIG. 2, FIG. 3, 2 ) and the semiconductor device ( Nakaoka, FIG. 3, 6 ) with the resin paste ( Nakaoka, FIG. 3, 41 ), wherein in plan view, the four grooves ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9; FIG. 3(a)-2 ) are present ( Nakaoka, FIG. 3 ) in centers of sides of the bonded semiconductor device( Nakaoka, FIG. 3, 6 ) and are absent ( Nakaoka, FIG. 3 ) at both ends of the sides of the semiconductor device ( Nakaoka, FIG. 3, 6 ). Nakaoka does not explicitly disclose: a step of discharging resin paste to a range including a center of the quadrangle formed by the four grooves and not including the four grooves; However, Nakaoka discloses: a step of discharging resin paste ( Nakaoka, FIG. 5(a) – 1, FIG. 5(a) – 2, 41 ) to a range including a center of the die pad ( Nakaoka, FIG. 5(a) – 1, FIG. 5(a) – 2, 2 ) and not including the four grooves; It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to create “ a step of discharging resin paste to a range including a center of the quadrangle formed by the four grooves and not including the four grooves ”, by duplicating the process of “ a step of discharging resin paste to a range including a center of the die pad and not including the four grooves ”, since this is conventional way of discharging resin paste, and within the skill level of one in the art. Claims 1 – 2, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Nakaoka ( Pub. No. JP H02288241 A ), hereinafter Nakaoka, in view of Moon ( Pat. No. US 5971734 A ), herein after Moon. Regarding Independent Claim 1, Nakaoka teaches a semiconductor manufacturing apparatus comprising: a nozzle ( Nakaoka, FIG. 1, 1; page 3, line 34, an adhesive discharging nozzle 1 ) including a cross groove ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9; page 3, line 35, a recess 9 in which two grooves intersect on the bottom surface ) provided on a bottom surface, a supply hole ( Nakaoka, FIG. 2(a), the center part filled with 41; page 4, line 9, A predetermined amount of conductive adhesive 41 is discharged ) provided in a center of the cross groove ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9 ), and a syringe ( Nakaoka, FIG. 1, 3; page 3, line 34, An adhesive container 3 ) configured to store resin paste ( Nakaoka, FIG. 1, 4; page 3, line 34, a conductive adhesive 4 ) and connected to the nozzle ( Nakaoka, FIG. 1, 1 ); and a dispenser ( Nakaoka, FIG. 1, 5; page 3, line 36, A type liquid 36 metering discharge device 5 ) configured to fill, in the cross groove ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9 ), the resin paste ( Nakaoka, FIG. 1, 4 ) in the syringe ( Nakaoka, FIG. 1, 3 ) via the supply hole ( Nakaoka, FIG. 2(a) ) with a gas pressure or an air pressure ( Nakaoka, FIG. 1, FIG. 2(c), FIG. 2(d); page 4, line 8, In this state, the pneumatic liquid metering discharge device 5 shown in FIG. 1 is operated, and as shown in FIG. A ( ps. this should be FIG. 2(c) and FIG. 2(d) ) predetermined amount of conductive adhesive 41 is discharged. ). Nakaoka fails to disclose: exhaust grooves that extend from ends of the cross groove to an outside of the bottom surface on the bottom surface and are shallower than the cross groove. However, Moon teaches: exhaust grooves ( Moon, FIG. 19, AV, D; col. 20, line 46, Air vents AV are formed at the remaining three corners of each concave portion 45 ) that extend from ends of the cross groove ( FIG. 19 – 20, cavities CV ) to an outside of the bottom surface on the bottom surface ( Moon, FIG. 17, FIG. 20, 40A; col. 20, line 44, a bottom cavity insert 40A ) and are shallower ( Moon, FIG. 19, AV, D; col. 20, line 67, The depth D of each air vent AV corresponds to about 0.5 to 15% of the depth D1 of the concave portion 45 ) than the cross groove ( FIG. 19 – 20, cavities CV ). Nakaoka and Moon are both considered to be analogous to the claimed invention because they are forming resin bonding or bonding agent for semiconductor chips. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakaoka ( a cross groove ( FIG. 1(b), 7; FIG. 2(a), 9 ) ), to incorporate the teachings of Moon ( FIG. 19, AV, D; col. 20, line 67, The depth D of each air vent AV corresponds to about 0.5 to 15% of the depth D1 of the concave portion 45 ), to add Moon’s AV to the end of Nakaoka’s cross groove as the exhaust grooves, and therefore implement exhaust grooves that extend from ends of the cross groove to an outside of the bottom surface on the bottom surface and are shallower ( Moon, FIG. 19, D ) than the cross groove. Doing so would provide that each air vent AV has a predetermined depth ( Moon, FIG. 19, D ) in order to achieve a good air ventilation while minimizing the leakage of resin through the air vent AV, therefore the air existing in cavities are smoothly and uniformly vented, and a desirable resin filling profile is exhibited. Regarding Claim 2, Nakaoka and Moon teach the semiconductor manufacturing apparatus as claimed in claim 1, on which this claim is dependent, Nakaoka and Moon further teach: wherein the bottom surface ( Nakaoka, FIG. 1(b), 7 is on the bottom surface of 1; FIG. 2(a), 9 is on the bottom surface of 1; page 3, line 35, a recess 9 in which two grooves intersect on the bottom surface ) is a quadrangle ( Nakaoka, FIG. 1 (b) ), corners of which are round-chamfered ( Moon, FIG. 17, 18A, 18B, corners of AV are round-chamfered ), and the cross groove ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9 ) and the exhaust grooves ( Moon, FIG. 17 – 20, AV ) are formed on diagonal lines of the quadrangle ( Nakaoka, FIG. 1 (b) ). Regarding Independent Claim 5, Nakaoka teaches a method of manufacturing a semiconductor apparatus comprising: a step of bringing a bottom surface of a nozzle ( Nakaoka, FIG. 1, 1; FIG. 2(a) – 2(d), 1; page 3, line 34, an adhesive discharging nozzle 1 ) into contact ( Nakaoka, FIG. 2(b), 1 contacts 2 ) with an application target object ( Nakaoka, FIG. 2(b), 2 ), the nozzle ( Nakaoka, FIG. 1, 1; FIG. 2(a) – 2(d), 1 ) including a cross groove ( Nakaoka, FIG. 1, 7; FIG. 2(a), 9; page 3, line 35, a recess 9 in which two grooves intersect on the bottom surface ) provided on the bottom surface, a supply hole ( Nakaoka, FIG. 2(a), the center part filled with 41; page 4, line 9, A predetermined amount of conductive adhesive 41 is discharged ) provided in a center of the cross groove ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9 ), and a step of filling ( Nakaoka, FIG. 2(c), FIG. 2(d) ) resin paste ( Nakaoka, FIG. 1, 4; FIG. 2(c), FIG. 2(d), 41; page 3, line 34, a conductive adhesive 4 ) in the cross groove ( Nakaoka, FIG. 1(b), 7; FIG. 2(a), 9 ) from the supply hole ( Nakaoka, FIG. 2(a) ) with a gas pressure or an air pressure ( Nakaoka, FIG. 1, 5; FIG. 2(c), FIG. 2(d); page 4, line 8, In this state, the pneumatic liquid metering discharge device 5 shown in FIG. 1 is operated, and as shown in FIG. A ( ps. this should be FIG. 2(c) and FIG. 2(d) ) predetermined amount of conductive adhesive 41 is discharged. ); a step of separating ( Nakaoka, FIG. 2(d) ) the nozzle ( FIG. 2(a) – 2(d), 1 ) from the application target object ( Nakaoka, FIG. 2(d), 2 ) and discharging the resin paste ( Nakaoka, FIG. 2(d), 41 ) having a cross shape ( Nakaoka, FIG. 3(a)-1, FIG. 3(a)-2, 41 ) to the application target object ( Nakaoka, FIG. 3(a)-1, FIG. 3(a)-2, 2 ); and a step of bonding ( Nakaoka, FIG. 3(a) – 3(b) ) a semiconductor device ( Nakaoka, FIG. 1(a), 2; FIG. 3(a) – 3(c), 2 ), which is a quadrangle ( Nakaoka, FIG. 1(b), 7; FIG. 2(b), 9; page 4, line 28, an X shape with two lines is shown as the shape of the concave 28 portion 9 ) in plan view, such that vertexes of the quadrangle ( Nakaoka, FIG. 1(b), 7; FIG. 2(b), 9 ) and ends of a cross of the resin paste discharged ( Nakaoka, FIG. 1(a), X shape on 2; FIG. 3(a), 41 on 2 ) in the cross shape coincide ( Nakaoka, “ 7 in FIG. 1(b) ” coincides “ X shape on 2 in FIG. 1(a) ” ) ( Nakaoka, page 4, line 21, First, FIG. 3(a) shows a state in which the conductive adhesive 41 is applied onto the die pad 2, and is applied in the shape of two intersecting lines. Next, in FIG. 3(b), the semiconductor chip 6 is transferred above the conductive adhesive 41, and the conductive adhesive 41 is slightly expanded by the weight of the semiconductor chip 6. Thereafter, in FIG. 3(e) ( ps. this should be FIG. 3(c) ), the semiconductor chip 6 is pressurized from above, so that the conductive adhesive 41 is uniformly spread over the entire back surface of the semiconductor chip 6 without generating bubbles. This pressurizing force may be about 30g ). Nakaoka fails to disclose: exhaust grooves that extend from ends of the cross groove to an outside of the bottom surface on the bottom surface and are shallower than the cross groove. However, Moon teaches: exhaust grooves ( Moon, FIG. 19, AV, D; col. 20, line 46, Air vents AV are formed at the remaining three corners of each concave portion 45 ) that extend from ends of the cross groove ( FIG. 19 – 20, cavities CV ) to an outside of the bottom surface on the bottom surface ( Moon, FIG. 17, FIG. 20, 40A; col. 20, line 44, a bottom cavity insert 40A ) and are shallower ( Moon, FIG. 19, AV, D; col. 20, line 67, The depth D of each air vent AV corresponds to about 0.5 to 15% of the depth D1 of the concave portion 45 ) than the cross groove ( FIG. 19 – 20, cavities CV ). Nakaoka and Moon are both considered to be analogous to the claimed invention because they are forming resin bonding or bonding agent for semiconductor chips. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakaoka ( a cross groove ( FIG. 1(b), 7; FIG. 2(a), 9 ) ), to incorporate the teachings of Moon ( FIG. 19, AV, D; col. 20, line 67, The depth D of each air vent AV corresponds to about 0.5 to 15% of the depth D1 of the concave portion 45 ), to add Moon’s AV to the end of Nakaoka’s cross groove as the exhaust grooves, and therefore implement exhaust grooves that extend from ends of the cross groove to an outside of the bottom surface on the bottom surface and are shallower ( Moon, FIG. 19, D ) than the cross groove. Doing so would provide that each air vent AV has a predetermined depth ( Moon, FIG. 19, D ) in order to achieve a good air ventilation while minimizing the leakage of resin through the air vent AV, therefore the air existing in cavities are smoothly and uniformly vented, and a desirable resin filling profile is exhibited. Claims 3 – 4 are rejected under 35 U.S.C. 103 as being unpatentable over Nakaoka, in view of Moon, further in view of Poerrer ( Pub. No. US 20130267062 A1 ), hereinafter Poerrer. Regarding Claim 3, Nakaoka and Moon teach the semiconductor manufacturing apparatus as claimed in claim 1, on which this claim is dependent, Nakaoka and Moon do not teach: wherein the nozzle includes one or more pins projecting from a periphery of the bottom surface or from the bottom surface, the pins projecting by 40 to 100 μm from the bottom surface. However, Poerrer teaches: wherein the nozzle includes one or more pins ( Poerrer, FIG. 2A, 210; [0033], protrusion element 210 ) projecting from a periphery of the bottom surface or from the bottom surface, the pins projecting by 40 to 100 μm ( Poerrer, FIG. 2A, 210; [0033], protrusion element 210; [0038], For dispensing distances in the range of 100 to 300 micrometers, for example around 170 micrometer, the length of pin-like protrusion elements such as downholder pin 210 results accordingly ) from the bottom surface. Nakaoka, Moon and Poerrer are all considered to be analogous to the claimed invention because they are forming resin bonding or adhesive mounting for semiconductor chips. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakaoka ( a cross groove ) and Moon ( The depth D of each air vent AV corresponds to about 0.5 to 15% of the depth D1 of the concave portion 45 ), to incorporate the teachings of Poerrer ( protrusion element 210 or downholder pin 210, and dispensing distances in the range of 100 to 300 micrometers ), to implement that pins projecting by 40 to 100 μm from the bottom surface. Doing so would provide an adjustable dispensing distance between dispensing outlet and carrier, and therefore to control the amount of deposited material ( Poerrer, [0022] ) for resin bonding or adhesive mounting of semiconductor chips. Regarding Claim 4, Nakaoka and Moon teach the semiconductor manufacturing apparatus as claimed in claim 2, on which this claim is dependent, Nakaoka and Moon do not teach: wherein the nozzle includes one or more pins projecting from a periphery of the bottom surface or from the bottom surface, the pins projecting by 40 to 100 μm from the bottom surface. However, Poerrer teaches: wherein the nozzle includes one or more pins ( Poerrer, FIG. 2A, 210; [0033], protrusion element 210 ) projecting from a periphery of the bottom surface or from the bottom surface, the pins projecting by 40 to 100 μm ( Poerrer, FIG. 2A, 210; [0033], protrusion element 210; [0038], For dispensing distances in the range of 100 to 300 micrometers, for example around 170 micrometer, the length of pin-like protrusion elements such as downholder pin 210 results accordingly ) from the bottom surface. Nakaoka, Moon and Poerrer are all considered to be analogous to the claimed invention because they are forming resin bonding or adhesive mounting for semiconductor chips. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakaoka ( a cross groove ) and Moon ( The depth D of each air vent AV corresponds to about 0.5 to 15% of the depth D1 of the concave portion 45 ), to incorporate the teachings of Poerrer ( protrusion element 210 or downholder pin 210, and dispensing distances in the range of 100 to 300 micrometers ), to implement that pins projecting by 40 to 100 μm from the bottom surface. Doing so would provide an adjustable dispensing distance between dispensing outlet and carrier, and therefore to control the amount of deposited material ( Poerrer, [0022] ) for resin bonding or adhesive mounting of semiconductor chips. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is (703)756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DA-WEI LEE/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jun 06, 2024
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
96%
With Interview (+15.4%)
3y 6m (~1y 2m remaining)
Median Time to Grant
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