DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 16 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2022/0271045 A1 to DING et al., “Ding”.
Regarding claim 11, Ding discloses a semiconductor device (e.g. FIG. 3E), comprising:
a substrate (100, ¶ [0032]);
a first insulating layer (140, ¶ [0060]) disposed (indirectly) on a first surface of the substrate (100);
a through via (TCT, ¶ [0076]-[0082]) penetrating the substrate (100) and the first insulating layer (140);
a protective barrier wall pattern (PIP, ¶ [0080]-[0081]) disposed within the first insulating layer (140) and at least partially covering a sidewall of an upper portion of the through via (near TCTt); and
a first wiring structure (M1, ¶ [0070]) disposed within the first insulating layer (140) and including a first via portion (VI) and a first wiring portion (INL), wherein an outer sidewall of the protective barrier wall pattern (PIP) is horizontally spaced apart from a sidewall of the first wiring portion (INL).
Regarding claim 16, Ding anticipates the semiconductor device of claim 11, and Ding further discloses (FIG. 3E) wherein the upper surface of the protective barrier wall pattern (PIP) is coplanar with an upper surface of the first insulating layer (the upper surface of 140 in recess with TCTt, see Examiner-annotated figure below).
PNG
media_image1.png
224
756
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10,12,14-15 are rejected under 35 U.S.C. § 103 as being unpatentable over US 2022/0271045 A1 to DING et al., “Ding”, in view of US 2009/0315154 A1 to Kirby et al., “Kirby”.
Regarding claim 1, Ding discloses a semiconductor device (e.g. FIG. 3E), comprising:
a semiconductor substrate (100, ¶ [0032]);
a first insulating layer (140, ¶ [0060]) disposed (indirectly) on a first surface of the semiconductor substrate (100);
a through via (TCT, ¶ [0076]-[0082]) passing through both the semiconductor substrate (100) and the first insulating layer (140);
a protective barrier wall pattern (PIP, ¶ [0080]-[0081]) disposed within the first insulating layer (140) and on a sidewall of the through via (TCT);
a first wiring structure (M1, ¶ [0070]) disposed within the first insulating layer (140) and including a first via portion (VI) and a first wiring portion (INL).
Ding fails to clearly teach a second insulating layer disposed on an upper surface of the first insulating layer and at least partially covering an upper surface of the first wiring structure and an upper surface of the protective barrier wall pattern.
Kirby teaches (FIG. 14) a second insulating layer (310, ¶ [0023],[0024]) disposed on an upper surface of a first insulating layer (e.g. 260, ¶ [0022]) and at least partially covering an upper surface of a first wiring structure (300) and an upper surface of sidewalls of a through-via (254, ¶ [0014],[0025]-[0026]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ding with a second level wiring connecting the active devices with the through-via as exemplified by Kirby in order to desirably route the connections from the source/drain regions to the backside of the device (Kirby ¶ [0014]) with benefits such as tighter pitch via formation, lower resistance than poly-Si interconnects, and an improved integration into semiconductor fabrication operations (Kirby ¶ [0013]).
Regarding claim 2, Ding in view of Kirby yields the semiconductor device of claim 1, and Kirby further teaches a second through wiring structure (320, ¶ [0024]) disposed within the second insulating layer (310) and electrically connected to the through via (through vias 312 formed in FIG. 12), wherein the second through wiring structure includes:
a plurality of second via portions (filled portions of 312 in FIG. 12 to FIG. 13, ¶ [0023]) laterally spaced apart from each other; and
a second wiring portion (upper portion of 320) disposed on the plurality of second via portions and electrically connected to the plurality of second via portions.
Regarding claim 3, Ding in view of Kirby yields the semiconductor device of claim 2, and Kirby further teaches wherein the second insulating layer (310) is further disposed between the plurality of second via portions (lower portions of 320 formed in FIG. 12 openings 312).
Regarding claim 4, Ding in view of Kirby yields the semiconductor device of claim 3, and Kirby further teaches wherein the second insulating layer (310) further covers at least a portion of an upper surface of the through via (254).
Regarding claim 5, Ding in view of Kirby yields the semiconductor device of claim 1, and Ding further teaches wherein an upper surface of the protective barrier wall pattern (PIP) is coplanar with an upper surface of the through via (TCT, see Examiner-annotated figure below).
PNG
media_image1.png
224
756
media_image1.png
Greyscale
Regarding claim 6, Ding in view of Kirby yields the semiconductor device of claim 1, and Ding further teaches (FIG. 3E) a lower insulating layer (130, ¶ [0060]) disposed between the semiconductor substrate (100) and the first insulating layer (140), wherein the through via (TCT) further passes through the lower insulating layer (130), and the protective barrier wall pattern (PIP) does not extend between the lower insulating layer (130) and the through via (TCT).
Regarding claim 7, Ding in view of Kirby yields the semiconductor device of claim 1, and Ding further teaches (FIG. 3E) wherein the first insulating layer (140) includes: a first etch stop layer (ESL, ¶ [0069]); and a first interlayer insulating layer (140) disposed on the first etch stop layer (ESL), wherein the protective barrier wall pattern (PIP) is disposed on an upper surface of the first etch stop layer (ESL), and the first via portion (VI) passes through the first etch stop layer (ESL).
Regarding claim 8, although Ding in view of Kirby yields the semiconductor device of claim 7, Ding fails to clearly anticipate wherein the first etch stop layer (ESL) includes a material that is different from a material of the protective barrier wall pattern (PIP).
However, Ding teaches wherein the first etch stop layer (ESL) may be a silicon nitride layer or a silicon oxide layer (¶ [0069]) and wherein the protective barrier wall pattern (PIP) may be at least one of SiN, SiCN, or SiON (¶ [0080]) which includes materials which are different from each other.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ding in view of Kirby with the materials for the etch stop layer and the protective barrier wall pattern being different since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
wherein in the instant case one having ordinary skill in the art would have been capable of and would have found it obvious to select different materials as it would have been “Obvious to try” to select different materials from the selection of disclosed materials with the predictable and desired result of forming suitable etch-stop and protective barrier wall patterns.
Regarding claim 9, Ding in view of Kirby yields the semiconductor device of claim 1, and Kirby further teaches (FIG. 14) a second circuit wiring structure (portion of 320 to the left) disposed within the second insulating layer (310) and on an upper surface of a first wiring structure (300), and electrically connected to the first wiring structure (300); and a second through wiring structure (portion connecting 320 to 254) disposed within the second insulating layer (310) and on the through via (254), and electrically connected to the through via (254), wherein the second through wiring structure is laterally spaced apart from the second circuit wiring structure (see Examiner-annotated figure below).
PNG
media_image2.png
330
718
media_image2.png
Greyscale
Regarding claim 10, Ding in view of Kirby yields the semiconductor device of claim 9, and Ding further teaches integrated circuits (e.g. active regions AR, ¶ [0094]) disposed on the first surface of the semiconductor substrate (100), Kirby further teaches (when applied to Ding) wherein the second circuit wiring structure is electrically connected (through 210) to the integrated circuits (transistors 202, ¶ [0015]) through the first wiring structure.
Regarding claim 12, although Ding anticipates the semiconductor device of claim 11, Ding fails to clearly teach a second insulating layer disposed on the first insulating layer, wherein the second insulating layer covers an upper surface of the first wiring structure and an upper surface of the protective barrier wall pattern.
Kirby teaches (FIG. 14) a second insulating layer (310, ¶ [0023],[0024]) disposed on an upper surface of a first insulating layer (e.g. 260, ¶ [0022]) and at least partially covering an upper surface of a first wiring structure (300) and an upper surface of sidewalls of a through-via (254, ¶ [0014],[0025]-[0026]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Ding with a second level wiring connecting the active devices with the through-via as exemplified by Kirby in order to desirably route the connections from the source/drain regions to the backside of the device (Kirby ¶ [0014]) with benefits such as tighter pitch via formation, lower resistance than poly-Si interconnects, and an improved integration into semiconductor fabrication operations (Kirby ¶ [0013]).
Regarding claim 14, Ding in view of Kirby yields the semiconductor device of claim 12, and Kirby further teaches a second through wiring structure (320, ¶ [0024]) disposed within the second insulating layer (310) and electrically connected to the through via (through vias 312 formed in FIG. 12), wherein the second through wiring structure includes:
a plurality of second via portions (filled portions of 312 in FIG. 12 to FIG. 13, ¶ [0023]) laterally spaced apart from each other; and
a second wiring portion (upper portion of 320) disposed on the plurality of second via portions and electrically connected to the plurality of second via portions.
Regarding claim 15, Ding in view of Kirby yields the semiconductor device of claim 14, and Kirby further teaches wherein the second insulating layer (310) is further disposed between the plurality of second via portions (from openings 312 in FIG. 12) and between an upper surface of the through via (254) and a lower surface of the second wiring portion (320).
Allowable Subject Matter
Claims 17-20 are allowed.
Claim 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Ding teaches a protective barrier wall pattern as discussed above and prior art e.g. Kirby teaches a second interlayer insulating layer as discussed above.
However, prior art fails to reasonably teach or suggest wherein the second insulating layer includes a second etch stop layer and a second interlayer insulating layer disposed on the second etch stop layer, wherein the second etch stop layer is in physical contact with both the upper surface of the first wiring structure and the upper surface of the protective barrier wall pattern, as claimed in claim 13 together with all of the limitations of claims 11 and 12.
Additionally, prior art fails to reasonably teach or suggest: a third insulating layer at least partially covering an upper surface of the second insulating layer and an upper surface of the second wiring structure; a third wiring structure disposed within the third insulating layer and including a third via portion and a third wiring portion; a backside insulating layer disposed on a second surface of the semiconductor substrate; and a lower pad disposed within the backside insulating layer, wherein the through via includes: a conductive via electrically connected to the lower pad; a barrier layer disposed on a sidewall of the conductive via; and an isolation layer disposed between the semiconductor substrate and the barrier layer, between the lower insulating layer and the barrier layer, and between the first insulating layer and the barrier layer, and wherein the second wiring structure includes: a second circuit wiring structure disposed on an upper surface of the first wiring structure and electrically connected to the first wiring structure; and a second through wiring structure disposed on an upper surface of the through via and electrically connected to the through via, together with all of the other limitations of claim 17. Claims 18-20 are allowable insofar as they depend upon and include all of the limitations of allowable claim 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2022/0084908 A1 to Shih et al. teaches (Fig. 7A) a through-via (110) with an etch blocking layer (302, ¶ [0034]);
US 2021/0398879 A1 to HUANG et al. teaches (FIG. 1) a through-via (401) with a protection layer (501, ¶ [0066],[0067]);
US 2016/0268182 A1 to LEE et al. teaches (FIG. 2A) a through-via (140) with a buffer layer (112, ¶ [0074],[0075]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Eric A. Ward/Primary Examiner, Art Unit 2891
Prosecution Insights