Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 11/10/25. Claims 1-4, and 10-12 and 14 are pending in this application.
Information Disclosure Statement
The information disclosure statements filed on 03/18/25, 11/13/24, 06/06/24 has been received and is being considered.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1- 4 are rejected under 35 U.S.C. §103 as being unpatentable over Guo (CN 114582962 B) and further in view of Cao (US 9583480 B2).
Regarding claim 1, Guo at least at (Fig. 1) discloses: A column III nitride transistor comprising: a substrate (1); a buffer layer (3) positioned above the substrate, wherein the buffer layer comprises a column III nitride material (e.g. paragraph 47: GaN): a barrier layer (4) positioned immediately above the buffer layer, wherein the barrier layer comprises a column III nitride material (e.g. paragraph 47: AIGaN); a channel comprising a conductive two-dimensional electron gas formed in the buffer layer near a junction of the buffer layer and the barrier layer (e.g. paragraph 65); one or more column III nitride material layers (5-8) above the barrier layer, wherein a first segment and a second segment are defined by the barrier layer and/or the one or more column III nitride material layers above the barrier layer, wherein the first segment (e.g. with layers 3-4) has a first thickness and the second segment (e.g. with layers 3-6, or 3-8) has a second thickness, the first thickness being less than the second thickness, wherein the number of free electrons in the first segment is lower than the number of free electrons in the second segment, such that the 2DEG in the channel under the first segment has a lower density of electrons than the 2DEG in the channel under the second segment (paragraph 65); and a gate (11), a source (10), and a drain (12), each positioned above the buffer layer, wherein the gate is positioned over the barrier layer between the source and the drain.
However, Guo does not explicitly disclose wherein a first of the plurality of transistors having a gate positioned on the first segment is an enhancement mode transistor with a positive threshold voltage, and a second of the plurality of transistors having a gate positioned on the second segment is a depletion mode transistor having a negative threshold voltage.
However, Cao is directed towards GaN devices disclose wherein a first of the plurality of transistors having a gate positioned on the first segment is an enhancement mode transistor with a positive threshold voltage, and a second of the plurality of transistors having a gate positioned on the second segment is a depletion mode transistor having a negative threshold voltage. See col 3, ln 54-col 4, ln 10)1 Guo and Cao are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Guo with Cao. Guo and Cao may be combined by forming the device of Guo with Cao by forming the source drain regions with threshold voltages. Guo and Cao may be combined in order to reduce gate leakage.
Regarding claim 2, Guo discloses the transistor integrated circuit of claim 1, wherein the first segment is closer to the source than the second segment (see fig 1, where first segment 3-4 is close to source 10).
Regarding claim 3, Guo discloses the transistor integrated circuit of claim 1, wherein the one or more column III nitride material layers above the barrier layer comprise AlxInyGazN, where x + y + z = 1 (see claim 6 disclosing composition).
Regarding claim 4, Gup discloses the transistor integrated circuit of claim 1, wherein the one or more column III nitride material layers above the barrier layer comprise paired layers of GaN and AlGaN (see claim 4).
Claims 10 ,11, 12, and 14 are rejected under 35 U.S.C. §103 as being unpatentable over Curatola (US 2019280100) and further in view of Cao (US 9583480 B2).
Regarding claim 10, Curatola US (2019280100) (Fig. 1 and associated text) and Cao (US 9583480 B2)discloses:
A column III nitride transistor comprising: a substrate (116); a buffer layer (106) positioned above the substrate, wherein the buffer layer comprises a column III nitride material (e.g. paragraph 27: GaN); a barrier layer (108) positioned above the buffer layer, wherein the buffer layer comprises a column III nitride material (e.g. paragraph 27: AIGaN); a channel comprising a conductive two-dimensional electron gas (110) formed in the buffer layer near a junction of the buffer layer and the barrier layer; wherein the barrier layer has a first segment (136) with a first thickness and a second segment (138) with a second thickness, wherein the first thickness is less than the second thickness, wherein the number of free electrons in the first segment is lower than the number of free electrons in the second segment, such that a 2DEG density in the channel under the first segment is lower than a 2DEG density in the channel under the second segment (paragraph 39); and a gate (122), a source (120), and a drain (118), each positioned above the buffer layer, wherein the gate contact is positioned over the barrier layer between the source and the drain.
However, Curatola does not explicitly disclose wherein a first of the plurality of transistors having a gate positioned on the first segment is an enhancement mode transistor with a positive threshold voltage, and a second of the plurality of transistors having a gate positioned on the second segment is a depletion mode transistor having a negative threshold voltage.
However, Curatola is directed towards GaN devices disclose wherein a first of the plurality of transistors having a gate positioned on the first segment is an enhancement mode transistor with a positive threshold voltage, and a second of the plurality of transistors having a gate positioned on the second segment is a depletion mode transistor having a negative threshold voltage. See col 3, ln 54-col 4, ln 10)2. Curatola and Cao are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Curatola with Cao. Guo and Curatola may be combined by forming the device of Curatola with Cao by forming the source drain regions with threshold voltages. Curatola and Cao may be combined in order to reduce gate leakage.
Regarding claim 11, Curolata and Cao disclose the transistor integrated circuit of claim 10, wherein the first segment is closer to the source than the second segment (see fig 1 disclosing 124 is thinner at 136 as compared with 138).
Regarding claim 12, Curolata and Cao disclose the transistor integrated circuit of claim 10, wherein the barrier layer comprises AlGaN (see fig 1, and para [0027]).
Regarding claim 14, Curolata and Cao disclose the transistor integrated circuit of claim 12, wherein the barrier layer of the second transistor is doped with an n type dopant to increase the density of electrons in the 2DEG and decrease the threshold voltage of the transistor (see Curolata para [0026] disclosing decreasing metallic concentration, see also [0057]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
1 Cao discloses the thinner portion 104 of the barrier layer under gate 103 increases the value of the positive threshold voltage V.sub.Th. As shown in FIG. 1, the gate 103 extends the entire width of the gate contact recess 104. Similarly, to modulate the threshold voltage V.sub.Th of the depletion mode device 201, the barrier layer 304 includes thinner portion 204 (i.e., a gate contact portion 204) under the gate 203, relative to the portions of the barrier layer 204 not disposed under the gate 203. The thinner portion 204 of the barrier layer under the gate 203 decreases the value of the negative threshold voltage V.sub.Th. As shown in FIG. 1, the gate 203 extends the entire width of the gate contact recess 204.
2 Ibid.
Prosecution Insights