DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first physical path PHY1 and the second physical path PHY2 being spaced apart from each other based on the horizontal direction (which, per claim 11, which claim 16 depends from by way of claim 14, is the X direction because that is the direction that the first memory chip structure 100 is spaced apart from processor 400) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Currently, the drawings show PHY1 and PHY2 being spaced apart in the Y horizontal direction, not the X horizontal direction. Compare applicants’ Figures 1 and 8, with applicants’ Figure 2.
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Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Page 7, paragraph 42, line 3: Change “first” to “second”. Compare with line 2.
Appropriate correction is required.
Claim Objections
Claims 8, 9, and 14-18 are objected to because of the following informalities:
Claim 8, line 2: Change “that is distance” to “distance that is”.
Claim 9, line 3: Should “second memory chip structure” be “second interposer”?
Claim 14, line 2: Change “PHY” to “physical layer (PHY)”.
Claim 16, line 2: Is this “horizontal direction” the same as the horizontal direction defined in claim 11, line 5? It appears to be a different horizontal direction, because the processor and the first memory chip structure of claim 11 are separated in the X horizontal direction, but the first PHY and the second PHY are separated in the Y horizontal direction.
Claim 17, line 3: Should “third memory chip structure” be “third interposer”?
Claim 18 is objected to for depending from objected-to base claim 17.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 14, which depends from claim 11: Claim 11 requires: “wherein a first electrical path that electrically connects the processor with the first memory chip structure and a second electrical path that electrically connects the processor with the second memory chip structure are independent of each other.” Claim 14, which depends from claim 11, requires:
wherein the first interposer includes a first PHY that transmits and receives an electrical signal between the processor and the first memory chip structure, the second interposer includes a second PHY that transmits and receives an electrical signal between the processor and the second memory chip structure, and the first PHY and the second PHY are not electrically connected to each other.
(emphasis added).
This raises a question as to whether the first electrical path is the same as the first PHY, and whether the second electrical path is the same as the second PHY. Because the language is not clear, claim 14 is rejected as indefinite.
Claims 15-18 are rejected for depending from rejected base claim 14.
Regarding claim 16, which depends from claim 14, which depends from claim 11: Claim 11 defines a horizontal direction in which the processor and first memory chip structure are spaced apart. From the drawings, this horizontal direction is the X horizontal direction. Claim 16 states that first physical layer PHY1 and the second physical layer PHY2 are spaced apart from each other based on the horizontal direction, which would also be the X horizontal direction, but the drawings show PHY1 and PHY2 being spaced apart from each other in the Y horizontal direction. Because the use of the term “horizontal direction” appears to mean two different things, claim 16 is rejected as indefinite.
Allowable Subject Matter
Claims 1-7, 10-13, 19, and 20 are allowed.
Claims 8 and 9 stand objected to for informalities, but would be allowable if the informalities were addressed.
Claims 14-18 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Baek Figure 1A:
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Regarding claim 1: Baek, U.S. Pat. Pub. No. 2022/0028848, Figure 1A, discloses a semiconductor package comprising: a substrate (100) including a first surface extended in first and second directions that cross each other; a semiconductor chip (200) disposed on the substrate (100); a first memory chip structure (300) disposed on the substrate (100), and including a plurality of first memory chips (310, 320, 330, 340) that are stacked on each other in a third direction that is substantially perpendicular to the first and second directions; a first interposer (400) disposed on the semiconductor chip (200) and the first memory chip structure (300); a second memory chip structure (500) disposed on the first interposer (400), and including a plurality of second memory chips (510, 520, 530, 540) that are stacked on each other in the third direction. Baek specification ¶¶ 43-64. Baek does not disclose a heat dissipation structure disposed on the semiconductor chip, wherein a length of the heat dissipation structure is smaller than a length of the semiconductor chip based on the first direction. Baek does not discuss heat dissipation issues. No other reference was identified that would be suitable for combining with Baek to render obvious claim 1. For this reason, claim 1 is allowable.
Regarding claim 11: Baek Figure 1A discloses a semiconductor package comprising: a first interposer (100); a processor (200) disposed on the first interposer (100); a first memory chip structure (300) including a plurality of first memory chips (310, 320, 330, 340) that are spaced apart from the processor (200) in a horizontal direction on the first interposer (100) and are stacked on each other in a vertical direction; a second interposer (400) disposed on the processor (100) and the first memory chip structure (300); a second memory chip structure (500) disposed on the second interposer (400), and including a plurality of second memory chips (510, 520, 530, 540) that are stacked on each other in the vertical direction; wherein a first electrical path (PHY1) electrically connects the processor (200) with the first memory chip structure (300). Id. Baek does not disclose a heat dissipation structure disposed on the processor, wherein a first electrical path that electrically connects the processor with the first memory chip structure and a second electrical path that electrically connects the processor with the second memory chip structure are independent of each other. Baek does not discuss heat dissipation issues, and the first electrical path (PHY1) that electrically connects the processor (200) with the first memory chip structure (300) is not independent of the second electrical path (PHY2) that connects the processor (200) to the first interposer (100)—the first and second electrical paths (PHY1, PHY2) are electrically connected. No other reference was identified that would be suitable for combining with Baek to render obvious claim 11. For this reason, claim 11 is allowable.
Regarding claim 19: Baek Figure 1A discloses a semiconductor package comprising: a first interposer (100); a processor (200) disposed on the first interposer (100); a first memory chip structure (300) including a plurality of first memory chips (310, 320, 330, 340) that are spaced apart from the processor (200) on the first interposer (100) and are stacked on each other in a vertical direction; a second interposer (400) disposed on the processor (200) and the first memory chip structure (300); a second memory chip structure (500) disposed on the second interposer (400), and including a plurality of second memory chips (510, 520, 530, 540) that are stacked on each other in the vertical direction. Id. Baek does not disclose a dummy silicon chip disposed on the processor, wherein the processor includes a first region, in which the dummy silicon chip is formed, and a second region, in which the dummy silicon chip is not formed, and the second interposer is disposed in the second region without being disposed in the first region. No other reference was identified that would be suitable for combining with Baek to render obvious claim 19. For this reason, claim 19 is allowable.
With regard to claim 1: The claim has been found allowable because the prior art of record does not disclose “a heat dissipation structure disposed on the semiconductor chip, wherein a length of the heat dissipation structure is smaller than a length of the semiconductor chip based on the first direction”, in combination with the remaining limitations of the claim.
With regard to claims 2-10: The claims have been found allowable due to their dependency from claim 1 above.
With regard to claim 11: The claim has been found allowable because the prior art of record does not disclose “a heat dissipation structure disposed on the processor, wherein a first electrical path that electrically connects the processor with the first memory chip structure and a second electrical path that electrically connects the processor with the second memory chip structure are independent of each other”, in combination with the remaining limitations of the claim.
With regard to claims 12-18: The claims have been found allowable due to their dependency from claim 11 above.
With regard to claim 19: The claim has been found allowable because the prior art of record does not disclose “a dummy silicon chip disposed on the processor, wherein the processor includes a first region, in which the dummy silicon chip is formed, and a second region, in which the dummy silicon chip is not formed, and the second interposer is disposed in the second region without being disposed in the first region”, in combination with the remaining limitations of the claim.
With regard to claim 20: The claim has been found allowable due to its dependency from claim 19 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Victoria K. Hall/Primary Examiner, Art Unit 2897
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