Prosecution Insights
Last updated: April 19, 2026
Application No. 18/735,803

VARIABLE FAST LOOK NEIGHBOR AHEAD TO IMPROVE READ ACCURACY

Final Rejection §103
Filed
Jun 06, 2024
Examiner
COON, BRADLEY SCOTT
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sandisk Technologies LLC
OA Round
2 (Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
34 granted / 36 resolved
+26.4% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
22 currently pending
Career history
58
Total Applications
across all art units

Statute-Specific Performance

§103
54.4%
+14.4% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
19.8%
-20.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 36 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments 2. Applicant's arguments filed February 24, 2026, see pages 11-13, have been fully considered but they are not persuasive. 3. Applicant submits there is no teaching or suggestion in Song, et al (US 11342033 B1, hereinafter Song) of using sense time adjustment as a scheme for compensating for data retention or NWI (neighbor word line interference) effects and that Song is silent regarding temperature-based adjustment. However, the previous Office Action relies the combination of Song with Chen, et al (US 11139031 B1, hereinafter Chen) and Reusswig, et al (US 9672940 B1, hereinafter Reusswig) to provide these modifications. 4. Applicant asserts Chen addresses data retention by compensating for NWI via adjustments of sense time and bit line voltage bias, but entirely in the context of program verify operations, not a read operation. However, Chen’s read in a program verify operation is analogous in operation to the “pre-read” of Song and the present application. For example, Chen describes the program verify read operation in Col. 4, ll. 34-42: “Each programmed data state is associated with a verify voltage such that a memory cell with a given data state is considered to have completed programming when a sensing operation determines its threshold voltage (Vth) is above the associated verify voltage. A sensing operation can determine whether a memory cell has a Vth above the associated verify voltage by applying the associated verify voltage to the control gate and sensing a current through the memory cell.” In ¶ [0139], Applicant teaches concerning the “pre-read” operation of ¶ [0137-0138]: “…the controller may identify the data states of the memory cells included in each respective neighboring word line by performing one or more read operations (sometimes referred to as sense operations). The controller may, for example, perform a read operation to identify a data state of a memory cell…” Because reads during a program verify operation and during the “pre-read” of the present application both utilize a sensing operation to determine if a cell’s programmed threshold voltage exceeds a comparison voltage, one would expect Chen’s method of compensating for NWI by adjusting the sense time during the read of the selected word line during a program verify operation (Chen Col. 5, ll. 24-45; FIG. 15) to also work during the read of the selected word line during a read (or “pre-read”) operation (see also MPEP § 2143(I)(B)). Figure A, which follows, shows the general flows of Song, Chen, and Applicant to help illustrate how one of ordinary skill in the art could, in the combination of Song and Chen, derive the method of Applicant (excepting temperature, which is provided by combining Reusswig). PNG media_image1.png 1098 1253 media_image1.png Greyscale Figure A: Methods of Song (top left), Chen (top right), and Applicant (bottom) 5. Applicant submits that while Reusswig appears to teach sense time adjustment for read operations, the sense time adjustment is linked to bit error rate (BER) and/or temperature to maintain constant decode time for fast versus standard read-not as a compensation scheme for NWI or data retention and the sense time adjustment of Reusswig is used to control the speed/latency of decode at the system (controller) level to balance error correction workload and read timing, not for compensating for neighbor word line effects or zones/data-state-dependent compensation. However, according to MPEP § 2145(X)(C), a teaching, suggestion, or motivation to combine references that is found in the prior art is an appropriate rationale for determining obviousness. That Applicant’s desired effects may differ from the prior art’s motivation to combine does not render the prior art’s motivation inappropriate. 6. Applicant submits that Jia focuses on the use of data retention compensation schemes in NAND flash memory, but consistently describes compensation schemes in terms of applying different voltage levels specifically, varying the read pass voltage (VREADK) or read voltage (VCG) for different zones defined by neighboring word line (WL) data states, and there is no disclosure or suggestion in Jia that compensation schemes are modified dynamically or in response to temperature data, nor is there any evidence that zone/data-state dependent compensation is combined with temperature to affect any compensation parameter. Note, however, that Jia is used only to address dependent claims 5, 12, and 18. In the independent claims, essential features have already been “built” into the apparatus of Song (e.g., a data retention compensation scheme corresponding to a zone of a plurality of zones based on neighboring word lines adjacent to the selected word line) as modified by Chen (improving data retention by compensating for neighboring word line interference by adjusting the sense time) and Reusswig (adjusting the sense time according to a temperature of the memory apparatus). Jia adds to the memory apparatus the additional feature of data stored in the memory cells as a plurality of lower bits of a lower page and a plurality of middle bits of a middle page and a plurality of upper bits of an upper page encoded with a code scheme, the plurality of groupings of ones of the plurality of data states includes the lower page corresponding with the first data state and the fifth data state and the middle page corresponding with the second data state and the fourth data state and the sixth data state and the upper page corresponding with the third data state and the seventh data state (Jia ¶ [0157]). This modification can be added according to motivation provided by Jia (MPEP § 2145(X)(C)) as provided in the previous Office Action and does not require re-introducing or re-justifying the modifications already introduced by Chen and Reusswig to the memory apparatus of Song. Claim Rejections - 35 USC § 103 7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 8. Claims 1-4, 7-11, 14-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Song, et al (US 11342033 B1), hereinafter Song, in view of Chen, et al (US 11139031 B1), hereinafter Chen, and further in view of Reusswig, et al (US 9672940 B1), hereinafter Reusswig. Regarding independent claim 1, Song teaches a memory apparatus (Col. 1, ll. 35-38), comprising: memory cells (FIG. 2; Col. 5, ll. 61-62) each connected to one of a plurality of word lines (FIG. 2, WL0..WL15) and configured to retain a threshold voltage corresponding to one of a plurality of data states (FIGS. 9-11); and a control means (FIG. 1A, e.g., 110, 124, 128, 132) configured to: determine ones of the plurality of data states for the memory cells of a neighboring word line of the plurality of word lines adjacent to a selected word line of the plurality of word lines (Col. 1, ll. 44-48; FIG. 14, 1402) in a pre-read (Col. 2, ll. 64-65; FIG. 14), determine an adjusted sense time according to a zone of a plurality of zones identified for the memory cells of the neighboring word line adjacent each of the memory cells of the selected word line and the one of the plurality of data states targeted for the memory cells of the selected word line (Col. 1, ll. 44-65 teaches a data retention compensation scheme corresponding to a zone of a plurality of zones; FIG. 18 shows these “zones” are based on neighboring word lines (WLn+1, WLn-1) adjacent to the selected word line (WLn – see Col. 5, ll.26-27)), and perform a plurality of reads on the selected word line for each of a plurality of groupings of ones of the plurality of data states in a read operation using the adjusted sense time determined for each of the memory cells of the selected word line (Col. 5, ll. 47-50 teach “Each zone may correspond to a data retention compensation scheme and a read operation may be performed on WLn including applying each data retention compensation scheme corresponding to any zones identified.”). Song does not teach the “data retention compensation scheme” includes adjusting the sense time for each of the memory cells of the selected word line. Chen teaches improving data retention by compensating for neighboring word line interference (NWI) by adjusting the sense time (Col. 5, ll. 24-45; FIG. 15, 1802, describes the read operation of a neighboring word line that determines the sense time for the read of the selected word line during programming (FIG. 15, 1804, 1806; Col. 4, ll. 31-34) and is therefore analogous to “pre-read” of Song and the present application (see FIG. 14, 1402, and ¶ [0138] of the present application)). Song does not teach adjusting the sense time according to a temperature of the memory apparatus. Reusswig teaches adjusting the sense time according to a temperature of the memory apparatus (Col. 27, ll. 6-31; FIG. 19, 1080). Regarding independent claim 8, Song teaches a controller (FIG. 1A, 122) in communication with a memory apparatus (Col. 1, ll. 35-38) including memory cells (FIG. 2; Col. 5, ll. 61-62) each connected to one of a plurality of word lines (FIG. 2, WL0..WL15) and configured to retain a threshold voltage corresponding to one of a plurality of data states (FIGS. 9-11), the controller configured to: instruct the memory apparatus to determine ones of the plurality of data states for the memory cells of a neighboring word line of the plurality of word lines adjacent to a selected word line of the plurality of word lines (Col. 1, ll. 44-48; FIG. 14, 1402) in a pre-read (Col. 2, ll. 64-65; FIG. 14); instruct the memory apparatus to determine an adjusted sense time according to a zone of a plurality of zones identified for the memory cells of the neighboring word line adjacent each of the memory cells of the selected word line and the one of the plurality of data states targeted for the memory cells of the selected word line (Col. 1, ll. 44-65 teaches a data retention compensation scheme corresponding to a zone of a plurality of zones; FIG. 18 shows these “zones” are based on neighboring word lines (WLn+1, WLn-1) adjacent to the selected word line (WLn – see Col. 5, ll.26-27)); and instruct the memory apparatus to perform a plurality of reads on the selected word line for each of a plurality of groupings of ones of the plurality of data states in a read operation using the adjusted sense time determined for each of the memory cells of the selected word line (Col. 5, ll. 47-50 teach “Each zone may correspond to a data retention compensation scheme and a read operation may be performed on WLn including applying each data retention compensation scheme corresponding to any zones identified.”). Song does not teach the “data retention compensation scheme” includes adjusting the sense time for each of the memory cells of the selected word line. Chen teaches improving data retention by compensating for neighboring word line interference (NWI) by adjusting the sense time (Col. 5, ll. 24-45; FIG. 15, 1802, describes the read operation of a neighboring word line that determines the sense time for the read of the selected word line during programming (FIG. 15, 1804, 1806; Col. 4, ll. 31-34) and is therefore analogous to “pre-read” of Song and the present application (see FIG. 14, 1402, and ¶ [0138] of the present application)). Song does not teach adjusting the sense time according to a temperature of the memory apparatus. Reusswig teaches adjusting the sense time according to a temperature of the memory apparatus (Col. 27, ll. 6-31; FIG. 19, 1080). Regarding independent claim 14, Song teaches a method (e.g., FIG. 14) of operating a memory apparatus (Col. 1, ll. 35-38) including memory cells (FIG. 2; Col. 5, ll. 61-62) each connected to one of a plurality of word lines (FIG. 2, WL0..WL15) and configured to retain a threshold voltage corresponding to one of a plurality of data states (FIGS. 9-11), the method comprising the steps of: determining ones of the plurality of data states for the memory cells of a neighboring word line of the plurality of word lines adjacent to a selected word line of the plurality of word lines (Col. 1, ll. 44-48; FIG. 14, 1402) in a pre-read (Col. 2, ll. 64-65; FIG. 14); determining an adjusted sense time according to a zone of a plurality of zones identified for the memory cells of the neighboring word line adjacent each of the memory cells of the selected word line and the one of the plurality of data states targeted for the memory cells of the selected word line (Col. 1, ll. 44-65 teaches a data retention compensation scheme corresponding to a zone of a plurality of zones; FIG. 18 shows these “zones” are based on neighboring word lines (WLn+1, WLn-1) adjacent to the selected word line (WLn – see Col. 5, ll.26-27)); and performing a plurality of reads on the selected word line for each of a plurality of groupings of ones of the plurality of data states in a read operation using the adjusted sense time determined for each of the memory cells of the selected word line (Col. 5, ll. 47-50 teach “Each zone may correspond to a data retention compensation scheme and a read operation may be performed on WLn including applying each data retention compensation scheme corresponding to any zones identified.”). Song does not teach the “data retention compensation scheme” includes adjusting the sense time for each of the memory cells of the selected word line. Chen teaches improving data retention by compensating for neighboring word line interference (NWI) by adjusting the sense time (Col. 5, ll. 24-45; FIG. 15, 1802, describes the read operation of a neighboring word line that determines the sense time for the read of the selected word line during programming (FIG. 15, 1804, 1806; Col. 4, ll. 31-34) and is therefore analogous to “pre-read” of Song and the present application (see FIG. 14, 1402, and ¶ [0138] of the present application)). Song does not teach adjusting the sense time according to a temperature of the memory apparatus. Reusswig teaches adjusting the sense time according to a temperature of the memory apparatus (Col. 27, ll. 6-31; FIG. 19, 1080). Regarding claims 1, 8, and 14, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Chen into the method of Song to include adjusting the read sense time based on a pre-read of a neighboring word line (Col. 5, ll. 24-45; FIG. 15, 1802). The ordinary artisan would have been motivated to modify Song in the above manner for the purpose of compensating for neighboring word line interference (Col. 5, ll. 24-26). It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Reusswig into the method of Song to include adjusting the sense time according to a temperature of the memory apparatus (Col. 27, ll. 6-31). The ordinary artisan would have been motivated to modify Song in the above manner for the purpose of maintaining constant decode time (Col. 27, ll. 25-28; FIG. 19, 1080). Regarding claim 2, Song as modified by Chen and Reusswig teaches the limitations of claim 1. Song further teaches the plurality of word lines (FIG. 6B, e.g., WLL0..WLL10) and a plurality of dielectric layers (FIG. 6B, DL0..DL19) extend horizontally (FIG. 6B, y-direction, depicted as horizontal in the drawing) and overlay one another in an alternating fashion in a stack (FIG. 6B; Col. 13, ll. 56-58), memory holes (FIG. 6B, 618, 619; Col. 13, ll. 64-65) extend vertically (FIG. 6B, z-direction, depicted as vertical in the drawing) through the stack (FIG. 6B, holes 618 and 619 are shown extending through the stack), the memory cells (FIG. 6D, MC) are connected in series between a drain-side select gate transistor (FIG. 6B, e.g., SGD0) on a drain-side of each of the memory holes (FIG. 6B, drain end 615; Col. 14, l. 4) and a source-side select gate transistor (FIG. 6B, e.g., SGS0) on a source-side of each of the memory holes (FIG. 6B, source end 613; Col. 14, l. 3), the drain-side select gate (SGD) transistor of each of the memory holes is connected to one of a plurality of bit lines (FIG. 2, each SGD transistor is connected to one of bit lines BL0..BL13) and the source-side select gate (SGS) transistor of each of the memory holes is connected to a source line (FIG. 2, each SGS transistor is connected to source line 220; Col. 9, 56-58), the neighboring word line is immediately adjacent to and disposed vertically above the selected word line in the stack. Regarding claim 3, Song as modified by Chen and Reusswig teaches the limitations of claim 1. Song further teaches in FIG. 12B the plurality of zones includes a first zone (e.g., ZONE1) corresponding with the memory cells of the neighboring word line (e.g., WLn+1) having the threshold voltage associated with one group of the plurality of data states (e.g., threshold voltage associated with data state A) and a second zone (e.g., ZONE2) corresponding with the memory cells of the neighboring word line having the threshold voltage associated with another group of the plurality of data states (e.g., threshold voltage associated with data state E). Regarding claim 4, Song as modified by Chen and Reusswig teaches the limitations of claim 3. Reusswig further teaches the memory apparatus further includes a temperature determination circuit (FIG. 2, 113) configured to detect the temperature of the memory apparatus (Col. 3, ll. 47-49) and the control means is further configured to: determine the temperature of the memory apparatus using the temperature determination circuit (FIG. 16, 1004; Col. 24, ll. 52-55). Song as modified by Chen and Reusswig teaches determine the adjusted sense time for each one of the memory cells of the selected word line using the first zone delta sense time in response to one of the memory cells of the neighboring word line adjacent to the one of the memory cells of the selected word line having the threshold voltage associated with of the plurality of data states; and determine the adjusted sense time for each one of the memory cells of the selected word line using the second zone delta sense time in response to the one of the memory cells of the neighboring word line adjacent to the one of the memory cells of the selected word line having the threshold voltage associated with the another group of the plurality of data states (Song teaches in Col. 5, ll. 47-50, “Each zone may correspond to a data retention compensation scheme and a read operation may be performed on WLn including applying each data retention compensation scheme corresponding to any zones identified”; Chen teaches improving data retention by compensating for neighboring word line interference (NWI) by adjusting the sense time (Col. 5, ll. 24-45; FIG. 15, 1802, describes the read operation of a neighboring word line that determines the sense time for the read of the selected word line during programming (FIG. 15, 1804, 1806; Col. 4, ll. 31-34). That is, Song teaches a zone-specific compensation, and Chen teaches compensation by adjusting sense times, both based on a pre-read of an adjacent word line, and therefore Song as modified by Chen teaches different zones may utilize different sense time adjustments.). Song fails to show the claimed range of calculate a first zone delta sense time as a first zone sense temperature offset being equal to one plus a first zone temperature coefficient multiplied by a first temperature offset equal to the temperature of the memory apparatus minus eighty five, and calculate a second zone delta sense time as a second zone sense coefficient multiplied by a second zone sense temperature offset, the second zone sense temperature offset being equal to one plus a second zone temperature coefficient multiplied by a second temperature offset equal to the temperature of the memory apparatus minus eighty five. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical, which is lacking in the present disclosure (e.g., see ¶ [0161] and [0168], which merely assert the constants in these equations are the case). “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Regarding claim 7, Song as modified by Chen and Reusswig teaches the limitations of claim 3. Song as modified by Chen and Reusswig further teaches the control means is further configured to apply a single read voltage corresponding to one of the plurality of data states to the selected word line (Song, the example of FIG. 12A uses a read voltage associated with data corresponding to data state E to determine if the bit is associated with data states Er to D or data states E to G) while the memory cells associated with the first zone (Song, FIG. 12A, data states Er to D are in ZONE1) and the memory cells associated with the second zone (Song, FIG. 12A, data states E to G are in ZONE2) are read in turn using the adjusted sense time during the plurality of reads (Song, FIG. 14, 1406, teaches the read operation uses the compensation scheme corresponding to the identified zone for the selected word line; Reusswig, FIG. 11, teaches the adjusted sense time determined by a temperature-based compensation scheme is used during reading; Col. 22, ll. 47-55; see also FIG. 19, 1080; Col. 27, ll. 6-38). Regarding claim 9, Song as modified by Chen and Reusswig teaches the limitations of claim 8. Song further teaches the plurality of word lines (FIG. 6B, e.g., WLL0..WLL10) and a plurality of dielectric layers (FIG. 6B, DL0..DL19) extend horizontally (FIG. 6B, y-direction, depicted as horizontal in the drawing) and overlay one another in an alternating fashion in a stack (FIG. 6B; Col. 13, ll. 56-58), memory holes (FIG. 6B, 618, 619; Col. 13, ll. 64-65) extend vertically (FIG. 6B, z-direction, depicted as vertical in the drawing) through the stack (FIG. 6B, holes 618 and 619 are shown extending through the stack), the memory cells (FIG. 6D, MC) are connected in series between a drain-side select gate transistor (FIG. 6B, e.g., SGD0) on a drain-side of each of the memory holes (FIG. 6B, drain end 615; Col. 14, l. 4) and a source-side select gate transistor (FIG. 6B, e.g., SGS0) on a source-side of each of the memory holes (FIG. 6B, source end 613; Col. 14, l. 3), the drain-side select gate (SGD) transistor of each of the memory holes is connected to one of a plurality of bit lines (FIG. 2, each SGD transistor is connected to one of bit lines BL0..BL13) and the source-side select gate (SGS) transistor of each of the memory holes is connected to a source line (FIG. 2, each SGS transistor is connected to source line 220; Col. 9, 56-58), the neighboring word line is immediately adjacent to and disposed vertically above the selected word line in the stack. Regarding claim 10, Song as modified by Chen and Reusswig teaches the limitations of claim 8. Song further teaches in FIG. 12B the plurality of zones includes a first zone (e.g., ZONE1) corresponding with the memory cells of the neighboring word line (e.g., WLn+1) having the threshold voltage associated with one group of the plurality of data states (e.g., threshold voltage associated with data state A) and a second zone (e.g., ZONE2) corresponding with the memory cells of the neighboring word line having the threshold voltage associated with another group of the plurality of data states (e.g., threshold voltage associated with data state E). Regarding claim 11, Song as modified by Chen and Reusswig teaches the limitations of claim 10. Reusswig further teaches the memory apparatus further includes a temperature determination circuit (FIG. 2, 113) configured to detect the temperature of the memory apparatus (Col. 3, ll. 47-49) and the controller is further configured to: instruct the memory apparatus to determine the temperature of the memory apparatus using the temperature determination circuit (FIG. 16, 1004; Col. 24, ll. 52-55). Song as modified by Chen and Reusswig teaches determine the adjusted sense time for each one of the memory cells of the selected word line using the first zone delta sense time in response to one of the memory cells of the neighboring word line adjacent to the one of the memory cells of the selected word line having the threshold voltage associated with the one group of the plurality of data states; and determine the adjusted sense time for each one of the memory cells of the selected word line using the second zone delta sense time in response to the one of the memory cells of the neighboring word line adjacent to the one of the memory cells of the selected word line having the threshold voltage associated with the another group of the plurality of data states (Song teaches in Col. 5, ll. 47-50, “Each zone may correspond to a data retention compensation scheme and a read operation may be performed on WLn including applying each data retention compensation scheme corresponding to any zones identified”; Chen teaches improving data retention by compensating for neighboring word line interference (NWI) by adjusting the sense time (Col. 5, ll. 24-45; FIG. 15, 1802, describes the read operation of a neighboring word line that determines the sense time for the read of the selected word line during programming (FIG. 15, 1804, 1806; Col. 4, ll. 31-34). That is, Song teaches a zone-specific compensation, and Chen teaches compensation by adjusting sense times, both based on a pre-read of an adjacent word line, and therefore Song as modified by Chen teaches different zones may utilize different sense time adjustments.). Song fails to show the claimed range of calculate a first zone delta sense time as a first zone sense temperature offset being equal to one plus a first zone temperature coefficient multiplied by a first temperature offset equal to the temperature of the memory apparatus minus eighty five, and calculate a second zone delta sense time as a second zone sense coefficient multiplied by a second zone sense temperature offset, the second zone sense temperature offset being equal to one plus a second zone temperature coefficient multiplied by a second temperature offset equal to the temperature of the memory apparatus minus eighty five. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical, which is lacking in the present disclosure (e.g., see ¶ [0161] and [0168], which merely assert the constants in these equations are the case). “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Regarding claim 15, Song as modified by Chen and Reusswig teaches the limitations of claim 14. Song further teaches the plurality of word lines (FIG. 6B, WLL0..WLL10) and a plurality of dielectric layers (FIG. 6B, DL0..DL19) extend horizontally (FIG. 6B, y-direction, depicted as horizontal in the drawing) and overlay one another in an alternating fashion in a stack (FIG. 6B; Col. 13, ll. 56-58), memory holes (FIG. 6B, 618, 619; Col. 13, ll. 64-65) extend vertically (FIG. 6B, z-direction, depicted as vertical in the drawing) through the stack (FIG. 6B, holes 618 and 619 are shown extending through the stack), the memory cells (FIG. 6D, MC) are connected in series between a drain-side select gate transistor (FIG. 6B, e.g., SGD0) on a drain-side of each of the memory holes (FIG. 6B, drain end 615; Col. 14, l. 4) and a source-side select gate transistor (FIG. 6B, e.g., SGS0) on a source-side of each of the memory holes (FIG. 6B, source end 613; Col. 14, l. 3), the drain-side select gate (SGD) transistor of each of the memory holes is connected to one of a plurality of bit lines (FIG. 2, each SGD transistor is connected to one of bit lines BL0..BL13) and the source-side select gate (SGS) transistor of each of the memory holes is connected to a source line (FIG. 2, each SGS transistor is connected to source line 220; Col. 9, 56-58), the neighboring word line is immediately adjacent to and disposed vertically above the selected word line in the stack. Regarding claim 16, Song as modified by Chen and Reusswig teaches the limitations of claim 14. Song further teaches in FIG. 12B the plurality of zones includes a first zone (e.g., ZONE1) corresponding with the memory cells of the neighboring word line (e.g., WLn+1) having the threshold voltage associated with one group of the plurality of data states (e.g., threshold voltage associated with data state A) and a second zone (e.g., ZONE2) corresponding with the memory cells of the neighboring word line having the threshold voltage associated with another group of the plurality of data states (e.g., threshold voltage associated with data state E). Regarding claim 17, Song as modified by Chen and Reusswig teaches the limitations of claim 16. Reusswig further teaches the memory apparatus further includes a temperature determination circuit (FIG. 2, 113) configured to detect the temperature of the memory apparatus (Col. 3, ll. 47-49) and the method further includes the steps of: determining the temperature of the memory apparatus using the temperature determination circuit (FIG. 16, 1004; Col. 24, ll. 52-55). determining the adjusted sense time for each one of the memory cells of the selected word line using the first zone delta sense time in response to one of the memory cells of the neighboring word line adjacent to the one of the memory cells of the selected word line having the threshold voltage associated with the one group of the plurality of data states; and determining the adjusted sense time for each one of the memory cells of the selected word line using the second zone delta sense time in response to the one of the memory cells of the neighboring word line adjacent to the one of the memory cells of the selected word line having the threshold voltage associated with the another group of the plurality of data states (Song teaches in Col. 5, ll. 47-50, “Each zone may correspond to a data retention compensation scheme and a read operation may be performed on WLn including applying each data retention compensation scheme corresponding to any zones identified”; Chen teaches improving data retention by compensating for neighboring word line interference (NWI) by adjusting the sense time (Col. 5, ll. 24-45; FIG. 15, 1802, describes the read operation of a neighboring word line that determines the sense time for the read of the selected word line during programming (FIG. 15, 1804, 1806; Col. 4, ll. 31-34). That is, Song teaches a zone-specific compensation, and Chen teaches compensation by adjusting sense times, both based on a pre-read of an adjacent word line, and therefore Song as modified by Chen teaches different zones may utilize different sense time adjustments.). Song fails to show the claimed range of calculate a first zone delta sense time as a first zone sense temperature offset being equal to one plus a first zone temperature coefficient multiplied by a first temperature offset equal to the temperature of the memory apparatus minus eighty five, and calculate a second zone delta sense time as a second zone sense coefficient multiplied by a second zone sense temperature offset, the second zone sense temperature offset being equal to one plus a second zone temperature coefficient multiplied by a second temperature offset equal to the temperature of the memory apparatus minus eighty five. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical, which is lacking in the present disclosure (e.g., see ¶ [0161] and [0168], which merely assert the constants in these equations are the case). “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Regarding claim 20, Song as modified by Chen and Reusswig teaches the limitations of claim 16. Song as modified by Chen and Reusswig further teaches the step of applying a single read voltage corresponding to one of the plurality of data states to the selected word line (Song, the example of FIG. 12A uses a read voltage associated with data corresponding to data state E to determine if the bit is associated with data states Er to D or data states E to G) while the memory cells associated with the first zone (Song, FIG. 12A, cell data states Er to D are in ZONE1) and the memory cells associated with the second zone (Song, FIG. 12A, cell data states E to G are in ZONE2) are read in turn using the adjusted sense time during the plurality of reads (Song, FIG. 14, 1406, the read operation uses the compensation scheme corresponding to the identified zone for the selected word line; Reusswig FIG. 11, the adjusted sense time is used during reading based on a temperature-based compensation scheme; Col. 22, ll. 47-55; see also FIG. 19, 1080; Col. 27, ll. 6-38). 9. Claims 5, 12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Song, et al (US 11342033 B1), hereinafter Song, in view of Chen, et al (US 11139031 B1), hereinafter Chen, in view of Reusswig, et al (US 9672940 B1), hereinafter Reusswig, and further in view of Jia, et al (US 20240272796 A1), hereinafter Jia. Regarding claim 5, Song as modified by Chen and Reusswig teaches the limitations of claim 4. Song further teaches in FIG. 10 the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state (Er) and a first data state (A) and a second data state (B) and a third data state (C) and a fourth data state (D) and a fifth data state (E) and a sixth data state (F) and a seventh data state (G). Song further teaches in FIG. 12A the first zone (ZONE1) corresponds with the memory cells of the neighboring word line having the threshold voltage associated with the erased state and the first data state and the second data state and the third data state and the fourth data state, and the second zone (ZONE2) corresponds with the memory cells of the neighboring word line having the threshold voltage associated with the fifth data state and the sixth data state and the seventh data state. Song does not teach data stored in the memory cells is stored as a plurality of lower bits of a lower page and a plurality of middle bits of a middle page and a plurality of upper bits of an upper page encoded with a code scheme, the plurality of groupings of ones of the plurality of data states includes the lower page corresponding with the first data state and the fifth data state and the middle page corresponding with the second data state and the fourth data state and the sixth data state and the upper page corresponding with the third data state and the seventh data state. Jia teaches in ¶ [0157] data stored in the memory cells is stored as a plurality of lower bits of a lower page and a plurality of middle bits of a middle page and a plurality of upper bits of an upper page encoded with a code scheme, the plurality of groupings of ones of the plurality of data states includes the lower page corresponding with the first data state and the fifth data state and the middle page corresponding with the second data state and the fourth data state and the sixth data state and the upper page corresponding with the third data state and the seventh data state. Regarding claim 12, Song as modified by Chen and Reusswig teaches the limitations of claim 11. Song further teaches in FIG. 10 the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state (Er) and a first data state (A) and a second data state (B) and a third data state (C) and a fourth data state (D) and a fifth data state (E) and a sixth data state (F) and a seventh data state (G). Song further teaches in FIG. 12A the first zone (ZONE1) corresponds with the memory cells of the neighboring word line having the threshold voltage associated with the erased state and the first data state and the second data state and the third data state and the fourth data state, and the second zone (ZONE2) corresponds with the memory cells of the neighboring word line having the threshold voltage associated with the fifth data state and the sixth data state and the seventh data state. Song does not teach data stored in the memory cells is stored as a plurality of lower bits of a lower page and a plurality of middle bits of a middle page and a plurality of upper bits of an upper page encoded with a code scheme, the plurality of groupings of ones of the plurality of data states includes the lower page corresponding with the first data state and the fifth data state and the middle page corresponding with the second data state and the fourth data state and the sixth data state and the upper page corresponding with the third data state and the seventh data state. Jia teaches in ¶ [0157] data stored in the memory cells is stored as a plurality of lower bits of a lower page and a plurality of middle bits of a middle page and a plurality of upper bits of an upper page encoded with a code scheme, the plurality of groupings of ones of the plurality of data states includes the lower page corresponding with the first data state and the fifth data state and the middle page corresponding with the second data state and the fourth data state and the sixth data state and the upper page corresponding with the third data state and the seventh data state. Regarding claim 18, Song as modified by Chen and Reusswig teaches the limitations of claim 17. Song further teaches in FIG. 10 the plurality of data states includes, in order of the threshold voltage increasing in magnitude, an erased state (Er) and a first data state (A) and a second data state (B) and a third data state (C) and a fourth data state (D) and a fifth data state (E) and a sixth data state (F) and a seventh data state (G). Song further teaches in FIG. 12A the first zone (ZONE1) corresponds with the memory cells of the neighboring word line having the threshold voltage associated with the erased state and the first data state and the second data state and the third data state and the fourth data state, and the second zone (ZONE2) corresponds with the memory cells of the neighboring word line having the threshold voltage associated with the fifth data state and the sixth data state and the seventh data state. Song does not teach data stored in the memory cells is stored as a plurality of lower bits of a lower page and a plurality of middle bits of a middle page and a plurality of upper bits of an upper page encoded with a code scheme, the plurality of groupings of ones of the plurality of data states includes the lower page corresponding with the first data state and the fifth data state and the middle page corresponding with the second data state and the fourth data state and the sixth data state and the upper page corresponding with the third data state and the seventh data state. Jia teaches in ¶ [0157] data stored in the memory cells is stored as a plurality of lower bits of a lower page and a plurality of middle bits of a middle page and a plurality of upper bits of an upper page encoded with a code scheme, the plurality of groupings of ones of the plurality of data states includes the lower page corresponding with the first data state and the fifth data state and the middle page corresponding with the second data state and the fourth data state and the sixth data state and the upper page corresponding with the third data state and the seventh data state. Regarding claims 5, 12, and 18, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Jia into the method of Song to include storing as a plurality of lower bits of a lower page and a plurality of middle bits of a middle page and a plurality of upper bits of an upper page encoded with a code scheme of the lower page corresponding with the first data state and the fifth data state and the middle page corresponding with the second data state and the fourth data state and the sixth data state and the upper page corresponding with the third data state and the seventh data state (Jia ¶ [0157]). The ordinary artisan would have been motivated to modify Song in the above manner for the purpose of performing the plurality of reads on the selected word line for each of the lower page and the middle page and the upper page continuously (i.e., without the pre-read in between each page) in the read operation (Jia ¶ [0157]). Allowable Subject Matter 10. Claims 6, 13, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 11. The following is a statement of reasons for the indication of allowable subject matter. Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a coefficient look up table including values of the first zone sense coefficient and the first zone temperature coefficient and the second zone sense coefficient and the second zone temperature coefficient for each one of the plurality of data states possible for the memory cells of the selected word line and the control means is configured to: select the first zone sense coefficient and the first zone temperature coefficient from the coefficient look up table based on the one of the plurality of data states targeted for the memory cells of the selected word line and calculate the first zone delta sense time accordingly; and select the second zone sense coefficient and the second zone temperature coefficient from the coefficient look up table based on the one of the plurality of data states targeted for the memory cells of the selected word line and calculate the second zone delta sense time accordingly. Regarding claim 13, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a coefficient look up table including values of the first zone sense coefficient and the first zone temperature coefficient and the second zone sense coefficient and the second zone temperature coefficient for each one of the plurality of data states possible for the memory cells of the selected word line and the controller is configured to: select the first zone sense coefficient and the first zone temperature coefficient from the coefficient look up table based on the one of the plurality of data states targeted for the memory cells of the selected word line and calculate the first zone delta sense time accordingly; and select the second zone sense coefficient and the second zone temperature coefficient from the coefficient look up table based on the one of the plurality of data states targeted for the memory cells of the selected word line and calculate the second zone delta sense time accordingly. Regarding claim 19, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of a coefficient look up table including values of the first zone sense coefficient and the first zone temperature coefficient and the second zone sense coefficient and the second zone temperature coefficient for each one of the plurality of data states possible for the memory cells of the selected word line and the method further includes the steps of: selecting the first zone sense coefficient and the first zone temperature coefficient from the coefficient look up table based on the one of the plurality of data states targeted for the memory cells of the selected word line and calculate the first zone delta sense time accordingly; and selecting the second zone sense coefficient and the second zone temperature coefficient from the coefficient look up table based on the one of the plurality of data states targeted for the memory cells of the selected word line and calculate the second zone delta sense time accordingly. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.S.C./Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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Prosecution Timeline

Jun 06, 2024
Application Filed
Nov 25, 2025
Non-Final Rejection — §103
Feb 24, 2026
Response Filed
Mar 13, 2026
Final Rejection — §103 (current)

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2y 5m
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