Prosecution Insights
Last updated: October 01, 2026
Application No. 18/735,859

SIDEWALL PINCH-OFF OF WORK FUNCTION METAL

Non-Final OA §102
Filed
Jun 06, 2024
Examiner
SUN, YU-HSI DAVID
Art Unit
Tech Center
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
683 granted / 881 resolved
+17.5% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
31 currently pending
Career history
897
Total Applications
across all art units

Statute-Specific Performance

§101
3.5%
-36.5% vs TC avg
§103
46.3%
+6.3% vs TC avg
§102
22.5%
-17.5% vs TC avg
§112
19.9%
-20.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 881 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YU et al. (US PG Pub 2024/0113195, hereinafter Yu). Regarding claim 1, figure 1I of Yu discloses a semiconductor device, comprising: a first stacked set of field effect transistors (FETs)(on the left), including a first top FET and a first bottom FET; a second stacked set of FETs (in the middle), including a second top FET and a second bottom FET; and a dielectric barrier (142) between the first stacked set of FETs and the second stacked set of FETs, the dielectric barrier having a narrower width between the first top FET and the second top FET than between the first bottom FET and the second bottom FET. Regarding claim 7, figure 1I of Yu discloses the dielectric barrier (142) has a stepped profile between a narrower top portion and a thicker bottom portion. Regarding claim 8, figure 1I of Yu discloses a step of the stepped profile is at a height between the first top FET and the first bottom FET. Regarding claim 9, figure 1I of Yu discloses a shallow trench isolation (STI) structure (114) in a substrate (102) between the first stacked set of FETs and the second stacked set of FETs that is formed from a dielectric material different from a material of the dielectric barrier (142). Allowable Subject Matter Claims 10-20 are allowed. Regarding claim 10, the closest prior art of record, YU et al. (US PG Pub 2024/0113195), either singularly or in combination, does not disclose or suggest the combination of limitations including “a first stacked set of field effect transistors (FETs), including a first top FET with a top work function metal layer and a first bottom FET with a bottom work function metal layer; a second stacked set of FETs, including a second top FET and a second bottom FET; and a dielectric barrier between the first stacked set of FETs and the second stacked set of FETs, the dielectric barrier having a narrower width between the first top FET and the second top FET than between the first bottom FET and the second bottom FET, the top work function metal layer having a greater thickness between a channel of the first top FET and the dielectric barrier than a thickness of the bottom work function metal layer between a channel of the first bottom FET and the dielectric barrier”. Regarding claim 18, the closest prior art of record, YU et al. (US PG Pub 2024/0113195), either singularly or in combination, does not disclose or suggest the combination of limitations including “a semiconductor device, comprising: a first stacked set of field effect transistors (FETs), including a first top FET with a top work function metal layer and a first bottom FET with a bottom work function metal layer; a second stacked set of FETs, including a second top FET and a second bottom FET; a shallow trench isolation (STI) structure in a substrate between the first stacked set of FETs and the second stacked set of FETs; and a dielectric barrier on the STI structure, between the first stacked set of FETs and the second stacked set of FETs, the dielectric barrier including a dielectric material different from a material of the STI structure and having a narrower width between the first top FET and the second top FET than between the first bottom FET and the second bottom FET, the top work function metal layer having a greater thickness between a channel of the first top FET and the dielectric barrier than a thickness of the bottom work function metal layer between a channel of the first bottom FET and the dielectric barrier”. Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jun 06, 2024
Application Filed
Aug 12, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
86%
With Interview (+8.4%)
2y 8m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 881 resolved cases by this examiner. Grant probability derived from career allowance rate.

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