Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Election was made without traverse in the reply filed on 8/21/2026. Applicant has elected Group II, corresponding to claims 1-16. Invention Group I, corresponding to claims 17-20, is withdrawn from further consideration.
Information Disclosure Statement
The information disclosure statements (IDS) submitted up to this point have been considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
[0099] “memory slice 224” appears to be misnumbered
[0086] “horizontal tunnel 970” is described but not shown in the drawings
[0130] “some slit openings 718” appears to be misnumbered
Also claim 4 does not appear to be fully described in the specification, specifically the range of 1 to 10 conductive layers for the extension depth of the top select gate cuts.
Appropriate correction is required.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claims 7 and 15: one of the top select gate cuts goes across at least one row of the memory strings (in combination with claim 1 limitation: top select gate cuts extending through the stack structure, at least two of the top select gate cuts being disposed between adjacent slit structures)
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6, 8-12, 14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang-803 (US # 20190035803) in view of Zhang-753 (US # 20200135753, English-language equivalent of CN # 109564922).
Regarding Claim 1, Zhang-803 teaches a semiconductor structure (see Figs. 20 and corresponding text), comprising:
a stack structure comprising interleaved conductive layers and dielectric layers (alternating stack of insulating layers 32 and conductive layers 46, together with the overlying insulating cap layer 70, isolation spacer layer 270 and drain select gate electrode 146; Fig. 20A, [0159, 161, 206, 244]);
memory strings (memory opening fill structures 58) and slit structures (backside trenches 79) extending through the stack structure (shown in Figs. 4A, 16D, 20D; [0175, 203, 230]); and
top select gate cuts (drain select level isolation strips 72) extending through the stack structure, at least two of the top select gate cuts being disposed between adjacent slit structures (a set of three strips 72 located between one neighboring pair of backside trenches 79 in Fig. l 6E), wherein:
one of the memory strings comprises a memory film (memory film 50) and a channel layer (channel portion 60), and the memory film comprises a tunneling layer (56), a storage layer (54), and a blocking layer (52); and
each of the top select gate cuts has a width (shown)
Although Zhang-803 discloses much of the claimed invention, it does not explicitly teach the semiconductor structure, comprising the top select gate cuts wherein each of the top select gate cuts has the width being smaller than a diameter of the memory strings.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Zhang-753 is in the same or analogous field, and it teaches the semiconductor structure, comprising the top select gate cuts (TSG 90; see Fig. 1B) wherein each of the top select gate cuts has the width being smaller than a diameter of the memory strings ([0047]).
A person having ordinary skill in the art would have recognized that modifying the relative feature sizes of Zhang-803 with the ratio suggested by Zhang-753 would be obvious. Specifically, the modification suggested by Zhang-753 would be to employ a semiconductor structure, comprising the top select gate cuts wherein each of the top select gate cuts has the width being smaller than a diameter of the memory strings. The rationale for this obvious modification is that a thinner TSG provides an opportunity for higher memory cell density. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of decreasing sizes of memory features are well known in the art (see MPEP 2144.01).
Regarding Claim 2, Zhang-803 further teaches
the channel layer comprises silicon (Si) (601, 602; [0190, 194]);
the tunneling layer comprises at least one of silicon oxide or silicon nitride (56; [0189] describes silicon oxide, silicon nitride or silicon oxynitride);
the storage layer comprises at least one of silicon nitride, silicon oxynitride, or silicon (charge storage layer 54 including a silicon nitride layer; [0186]);
the blocking layer comprises at least one of silicon oxide, silicon nitride, or high dielectric constant (high-k) dielectrics (52; [0183-185] describe silicon oxide, silicon oxynitride, silicon nitride or a dielectric metal oxide).
Regarding Claim 3, Zhang-803 further teaches the conductive layers comprise tungsten (W) (layers 46 being a tungsten layer, [0242, 244]).
Regarding Claim 4, Zhang-803 further teaches the semiconductor structure of claim 1, wherein each of the top select gate cuts (72) comprises a dielectric structure (feature 72 is silicon oxide) in contact with the conductive layers (146) and dielectric layers (270), and one of the top select gate cuts extends through 1 to 10 of the conductive layers (shown extending through 146).
Regarding Claim 6, Zhang-803 further teaches the memory strings are arranged in rows, and each row of the memory strings is staggered from adjacent rows of the memory strings (two-dimensional array of memory openings 49 arranged in rows with an inter-row pitch p, adjacent rows being laterally offset; Figs. 4B, 16, [0205]).
Regarding Claim 8, Zhang-803 further teaches at least two of the top select gate cuts extend parallel to the slit structures (isolation strips 72 extending along the first horizontal direction hd1, and backside trenches 79 extending along the same first horizontal direction hd1, parallel to the lengthwise direction of the strips 72; Figs. 16E, 20E, [0227, 231]).
Regarding Claim 9, Zhang-803 further teaches the semiconductor structure of claim 1, wherein the memory film is continuous (shown).
Regarding Claim 10, Zhang-803 teaches the semiconductor structure, comprising:
a stack structure (tungsten layer 46, insulating layers 32 of silicon oxide, together with layer 270 and electrode 146) comprising interleaved tungsten (W) layers (46) and silicon oxide layers (32; [0164, 206, 242, 244]);
memory strings (58) and slit structures (79) extending through the stack structure; and
top select gate cuts (72) extending through at least one of the W layers, at least two of the top select gate cuts being disposed between adjacent slit structures, wherein:
one of the memory strings comprises a memory film (50) and a channel layer (60), and the memory film comprises a tunneling layer (56), a storage layer (54), and a blocking layer (52);
the channel layer, the tunneling layer, the storage layer, and the blocking layer are all continuous (shown).
Although Zhang-803 discloses much of the claimed invention, it does not explicitly teach the semiconductor structure, comprising the top select gate cuts wherein each of the top select gate cuts has the width being smaller than a diameter of the memory strings.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Zhang-753 is in the same or analogous field, and it teaches the semiconductor structure, comprising the top select gate cuts (TSG 90; see Fig. 1B) wherein each of the top select gate cuts has the width being smaller than a diameter of the memory strings ([0047]).
A person having ordinary skill in the art would have recognized that modifying the relative feature sizes of Zhang-803 with the ratio suggested by Zhang-753 would be obvious. Specifically, the modification suggested by Zhang-753 would be to employ a semiconductor structure, comprising the top select gate cuts wherein each of the top select gate cuts has the width being smaller than a diameter of the memory strings. The rationale for this obvious modification is that a thinner TSG provides an opportunity for higher memory cell density. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of decreasing sizes of memory features are well known in the art (see MPEP 2144.01).
Regarding Claim 11, 12, 14, and 16, these claims are rejected for essentially the same reasons as claims 2, 3/4, 6, and 8 (respectively).
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang-803 (US # 20190035803) in view of Zhang-753 (US # 20200135753, English-language equivalent of CN # 109564922, which was cited in the IDS dated 06/06/2024) and further in view of Zhang-009 (US # 20180097009).
Regarding Claim 5, although Zhang-803 in view of Zhang-753 discloses much of the claimed invention, it does not explicitly teach the semiconductor structure of claim 1, wherein an insulating film covers sidewalls of the slit structures, and at least one of the slit structures further comprises a conductive core.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Zhang-009 is in the same or analogous field, and it teaches an insulating spacer (74) on the sidewalls of each backside trench ([0140]; Figs. 16A, 16B), and a backside contact via structure 76, having a conductive liner 76A and a conductive fill material portion 76B of W, Cu, Al, Co, Ru or Ni, formed within the insulating spacer 74 and extending through the alternating stack to contact a top surface of the source region 61 ([0144, 146]; Figs. 16A, 16B).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have provided the backside trenches of Zhang-803 with the insulating spacer and the conductive core, as taught by Zhang-009, because the arrangement provides a contact to the source region 61 through the backside trench while the insulating spacer 74 laterally surrounds the contact via structure 76 and separates it from the sidewalls of the electrically conductive layers 46 ([0140, 144, 146]). And Zhang-803 itself contemplates that its backside trenches can include a source contact opening in which a source contact via structure can be subsequently formed (Zhang-803 [0230]).
Regarding Claim 13, this claim is rejected for essentially the same reasons as claim 5.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang-803 (US # 20190035803) in view of Zhang-753 (US # 20200135753, English-language equivalent of CN # 109564922) and further in view of Zhang-382 (CN 109786382, which was cited in the IDS dated 06/06/2024).
Regarding Claim 7, although Zhang-803 in view of Zhang-753 discloses much of the claimed invention, it does not explicitly teach the semiconductor structure of claim 6, wherein one of the top select gate cuts goes across at least one row of the memory strings.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Zhang-382 is in the same or analogous field, and it teaches forming the array of channel structures 222 through the stack (Fig. 3, step 304; [0057-59]) and then forming a top select gate cut 203 between the first and second gate line slits 201, 202 over one row of that array, the channel structures beneath the cut being defined as dummy channel structures 222a (Fig. 3, step 308; Figs. 2, 4D; [0041, 71]), the finger then having thirteen rows of channel structures counting the row of dummy channel structures 222a beneath the cut 203 ([0044]).
A person having ordinary skill in the art before the effective filing date of the claimed invention would have placed one of the several drain select level isolation strips of Zhang-803 across a row of the memory openings 49, as taught by Zhang-382, the remaining strips staying between rows. This is because the row-crossing cut divides the finger into sub-regions whose top select gates can be controlled separately ([0036, 70]), which is the same function each isolation strip 72 performs in Zhang-803, where each lengthwise sidewall of a strip 72 contacts a respective drain select gate electrode 146 (Zhang-803 [0317]), and because forming the cut over a row after the channel structures are formed leaves the cut and its row of dummy channel structures 222a occurring only once for every several columns of channel structures, raising the proportion of effective channel structures and the storage density (Zhang-382 [0041]). The substitution of one known placement of a select gate cut for another, each performing the same dividing function, yields no more than the predictable result that the channel structures beneath the cut serve as dummy channel structures (Zhang-382 [0041, 71]). See MPEP 2143(I)(B).
Regarding Claim 15, this claim is rejected for essentially the same reasons as claim 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
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